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AM5K2E04: DDR3 layout

Danilo A.
Mastermind 34000 points

Part Number: AM5K2E04

Hi Team,

Our customer is using 5pcs. of DDR3 with AM5K2E04 processor. He routed the DDR3 as chip4, chip3, chip5, chip2, and chip0 and kept the termination resistor at chip1. Generally fly by topology say that routing of address, common, clock start from chip1, chip2, chip3, chip4 and chip5. When he did SI analysis, he didn't find any issues. He used the reference design of 66ak2h processor EVM layout from the link below.

e2e.ti.com/.../evmk2h-where-can-i-get-the-hardware-manual-for-evm-k2h-66ak2h-evaluation-modules

He would like to confirm if there would be an issue with this DDR3 layout.

Regards,

Danilo

  • 0
    TI__Guru* 85925 points

    Danilo

    I have reassigned this to my colleague , however they are out of office till Jan 5th. This will likely need to wait till they are back online. 

    I would encourage that the customer goes through the DDR design collateral , a good place to start is the Keystone 2 Hardware Design Guide

    https://www.ti.com/lit/an/sprabv0/sprabv0.pdf

    The DDR section has links to other application notes.

    The controller on K2H and K2E is similar and so are most of the layout out and topology guideslines, so my assumption is that if they see it working on K2H, it should also work for K2E family. 

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    TI__Mastermind 34000 points

    Hi Team,

    May we request an update regarding our customer's inquiry above.

    Thank you for your support!

    Regards,

    Danilo

  • 0 in reply to Danilo A.
    TI__Guru 56957 points

    Danilo,

    Is this a typo:

    DDR3 as chip4, chip3, chip5, chip2, and chip0 and kept the termination resistor at chip1

    Should be:

    DDR3 as chip4, chip3, chip5, chip2, and chip1 and kept the termination resistor at chip1

    Are you saying the EVM and the customer implementation is the same?

    Can you paste a snapshot of what the fly-by routing looks like?  In general, the routing  should not traverse around a memory and back.  You should take the shortest path from the first to the last memory.

    Regards,

    Kyle