Hi,
We designed a board with the omapL138 and a micron MT47H16M16 DDR2 RAM. I have problems in reading and or writing the ddr2. When I write 0xFFFFFFFF then it is oke but, when I write 0x00000000 then I see 0x04800480. It looks like there are some lines always high but this is not the case. When I do a read before I do I write in the same address space then it works normal, write 0x00000000 read 0x00000000. The DDR2 is connected according to the data sheet paragraph 6.1. The ddr is located very close to the omap. All the Voltages look oke. The ddr is running on 150MHz. The DDR2 initialization is done by the following gel file. Does somebody know what could be wrong?
// **********************************************************************************************
// 256Mb DDR MT47H16M16BG-3:B on dspboard
// Config DDR timings
DRPYC1R = (0x0 << 8) | // Reserved
(0x1 << 7) | // EXT_STRBEN
(0x0 << 6) | // PWRDNEN
(0x0 << 3) | // Reserved
(0x3 << 0); // RL RoundTrip latency= cl+1-1
if( DDR_DEBUG ) {
// Configure EMIF with max timings for more slack
// Try this if memory is not stable
DRPYC1R |= 0x8; // RL
}
// Settings that change depending on DDR2 or MDDR
if( ddr_type == DDR2 ) {
DDR_SLEW = 0x00000000; // Disable Pull Downs, Disable LVCMOS Rx
tmp_SDCR = (0x0 << 25) | // MSDRAMEN
(0x1 << 20); // DDR2EN
GEL_TextOut("\tUsing DDR2 settings\n","Output",1,1,1);
}
else if( ddr_type == MDDR ) {
DDR_SLEW = 0x00000030; // Enable Pull Downs, Enable LVCMOS Rx
tmp_SDCR = (0x1 << 25) | // MSDRAMEN
(0x0 << 20); // DDR2EN
GEL_TextOut("\tUsing mDDR settings\n","Output",1,1,1);
}
else {
DDR_SLEW = 0x00000030; // Enable Pull Downs, Enable LVCMOS Rx
tmp_SDCR = (0x1 << 25) | // MSDRAMEN
(0x0 << 20); // DDR2EN
GEL_TextOut("\tUnknown DDR Type! Using MDDR settings\n","Output",1,1,1);
}
EMIFDDR_SDCR |= 0x00800000; // Set BOOTUNLOCK
EMIFDDR_SDCR = tmp_SDCR | // Settings that change depending on DDR2 or MDDR
(EMIFDDR_SDCR & 0xF0000000) | // Reserved
(0x0 << 27) | // DDR2TERM1 = 0: ODT not supported by omap
(0x0 << 26) | // IBANK_POS = 0: normal addressing
(0x0 << 24) | // DDRDRIVE1 = 0: normal drive
(0x0 << 23) | // BOOTUNLOCK = 0: lock it again
(0x0 << 22) | // DDR2DDQS = 0: single ended DQS is supported by omap only
(0x0 << 21) | // DDR2TERM0 = 0: ODT not supported by omap
(0x0 << 19) | // DDRDLL_DIS = 0: enable DLL
(0x0 << 18) | // DDRDRIVE0 = 0: normal drive
(0x1 << 17) | // DDREN = 1: enable ddr
(0x1 << 16) | // SDRAMEN = 1: enable sdram
(0x1 << 15) | // TIMUNLOCK = 1: SDTIMR1 and 2 needs to be updated
(0x1 << 14) | // NM = 1: buswidth = 16b
(0x0 << 12) | // Reserved
(0x3 << 9) | // CL = 3: CAS latency =3 not sure because can be set by MR command
(0x0 << 7) | // Reserved
(0x2 << 4) | // IBANK = 2: 4 banks
(0x0 << 3) | // Reserved
(0x1 << 0); // PAGESIZE = 1 : 8 addr: 512 words
if( ddr_type == MDDR ) {
EMIFDDR_SDCR2 = 0x00000000; // IBANK_POS set to 0 so this register does not apply
}
// Let float -> integer truncate handle minus 1; Safer to round up for timings
// float values is ns
EMIFDDR_SDTIMR1 = (((unsigned int) ( 75.0 * freq / 1000)) << 25) | // tRFC : 75ns
(((unsigned int) ( 15.0 * freq / 1000)) << 22) | // tRP : 15ns
(((unsigned int) ( 15.0 * freq / 1000)) << 19) | // tRCD : 15ns
(((unsigned int) ( 15.0 * freq / 1000)) << 16) | // tWR : 15ns
(((unsigned int) ( 45.0 * freq / 1000)) << 11) | // tRAS : 45ns
(((unsigned int) ( 60.0 * freq / 1000)) << 6) | // tRC : 60ns
(((unsigned int) ( 7.5 * freq / 1000)) << 3) | // tRRD : 7.5ns
(EMIFDDR_SDTIMR1-1 & 0x4) | // Reserved ???
(((unsigned int) ( 7.5 * freq / 1000)) << 0); // tWTR : 7.5ns
EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000) | // Reserved //31-03-2011 changed by Roy
(((unsigned int) (70000 / 7812.5) ) << 27) | // tRASMAX : 70000
(0x2 << 25) | // tXP : 2 cycles (tcke-1)
(0x0 << 23) | // tODT (Not supported)
(((unsigned int) ( 85.0 * freq / 1000)) << 16) | // tXSNR : 75+10ns
( (unsigned int) (200) << 8) | // tXSRD : 200ck
(((unsigned int) ( 7.5 * freq / 1000)) << 5) | // tRTP : 7.5ns
((3 - 1) << 0); // tCKE : 3 ck
EMIFDDR_SDCR &= ~0x00008000; // Clear TIMUNLOCK
// Let float -> integer truncate handle RR round-down; Safer to round down for refresh rate
EMIFDDR_SDRCR = (0x0 << 31) | // LPMODEN (Required for LPSC SyncReset/Enable) =0: disable low power
(0x0 << 30) | // MCLKSTOPEN (Required for LPSC SyncReset/Enable)=0: MCLK will not be stopped
(0x0 << 24) | // Reserved
(0x0 << 23) | // SR_PD =0: dont care
(0x0 << 16) | // Reserved
(((unsigned int) (7.8125 * freq)) << 0); // RR =RR = 7.8125us
// SyncReset the Clock to EMIFDDR SDRAM
PSC1_LPSC_SyncReset(PD0, LPSC_DDR);
// Enable the Clock to EMIFDDR SDRAM
PSC1_LPSC_enable(PD0, LPSC_DDR);
// Disable self-refresh
EMIFDDR_SDRCR &= ~0xC0000000;
// SDRCR Value @ 150MHz = 0x00000493
// Set PBBPR to a value lower than default to prevent blocking
EMIFDDR_PBBPR = 0x30;
}
