TDA4VM: C66x PLL clock dynamic change in Linux

Karthik,

The thing is that using k3conf I can change every clock of TDA4VM exepct C66x domain.

Regards,

Alexey

Alexey,

Ah, ok.. this is strange.

Could you please share more details about what you have tried and how you verified that the C6x clock is not changing?

It would useful to clarify the SDK version that you are using as well. We will replicate the issue and enable you further.

Regards

Karthik

Karthik,

This is what I get:

root@j7-evm:/run/media/sdb# k3conf dump device 143
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-45-g79f007c built Thu Sep 2 18:06:41 UTC 2021)          |
| SoC    | J721E SR2.0                                                           |
| SYSFW  | ABI: 3.1 (firmware version 0x0015 '21.5.0--v2021.05 (Terrific Llam)') |
|--------------------------------------------------------------------------------|

|------------------------------------------------------|
| Device ID | Device Name            | Device Status   |
|------------------------------------------------------|
|   143     | J721E_DEV_C66SS1_CORE0 | DEVICE_STATE_ON |
|------------------------------------------------------|

root@j7-evm:/run/media/sdb# k3conf dump clock 143
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-45-g79f007c built Thu Sep 2 18:06:41 UTC 2021)          |
| SoC    | J721E SR2.0                                                           |
| SYSFW  | ABI: 3.1 (firmware version 0x0015 '21.5.0--v2021.05 (Terrific Llam)') |
|--------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                         | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------|
|   143     |     0    | DEV_C66SS1_CORE0_GEM_TRC_CLK       | CLK_STATE_READY | 0               |
|   143     |     1    | DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK  | CLK_STATE_READY | 0               |
|   143     |     4    | DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK | CLK_STATE_READY | 0               |
|   143     |     6    | DEV_C66SS1_CORE0_GEM_CLKIN_CLK     | CLK_STATE_READY | 1350000000      |
|-----------------------------------------------------------------------------------------------|

root@j7-evm:/run/media/sdb# k3conf set clock 143 6 1000000000
|--------------------------------------------------------------------------------|
| VERSION INFO                                                                   |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-45-g79f007c built Thu Sep 2 18:06:41 UTC 2021)          |
| SoC    | J721E SR2.0                                                           |
| SYSFW  | ABI: 3.1 (firmware version 0x0015 '21.5.0--v2021.05 (Terrific Llam)') |
|--------------------------------------------------------------------------------|

Invalid clock arguments

COMMANDS

        k3conf set clock <dev_id> <clk_id> <freq>
                Sets the clock frequency and prints the status

Regards,

Alexey

Hi Alexey,

I could reproduce the issue with k3confi that you have highlighted above.

I tried playing around a bit more and it works only with 1350000000 which is the default set frequency.

k3conf set clock 143 6 1350000000
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-45-g79f007c built Mon Dec 20 16:35:52 UTC 2021) |
| SoC | J721E SR1.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0015 '21.9.1--v2021.09a (Terrific Lla)') |
|--------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|-----------------------------------------------------------------------------------------------|
| 143 | 0 | DEV_C66SS1_CORE0_GEM_TRC_CLK | CLK_STATE_READY | 0 |
| 143 | 1 | DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK | CLK_STATE_READY | 0 |
| 143 | 4 | DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK | CLK_STATE_READY | 0 |
| 143 | 6 | DEV_C66SS1_CORE0_GEM_CLKIN_CLK | CLK_STATE_READY | 1350000000 |
|-----------------------------------------------------------------------------------------------|

What is your final intent. I need to check with our HW experts on what other frequencies C6x can run normally.
Can you describe your use case and what you are trying to achieve by reducing the C6x clock frequency?

- Keerthy

Keerthy,

My final usecase to extend working time by lowering freqency and power consumption of high current domains due to normally staying in stand-by (less than 3% of perfomance used) mode. The final goal to extend power consumption to one day of internal power reserve (3-4W/h).

Regards,

Alexey

Alexey,

Thanks for the detailed use case. I will check internally and get back if we can reduce the C6x clock frequency dynamically.

Best Regards,
Keerthy

Keerthy,

First try failed. After reboot this procedure started to work.

Thanks,

Alexey