TDA4VM: How to make DDR frequency operate normally at 4266MTS?

SandalHao

Part Number: TDA4VM

Hi,

We use TI's sdk7 2. There is no problem with the compiled bootloader running on the our custom TDA4 board.

But the following problems will occur when compiling and generating or the bootloader in the prebuilt SDK after using sdk7 3.

After using the tool to change the DDR frequency to 3732MTS with SDK7.3, our custom board can start normally.

So we started the sdk7.3 ddr frequency test, and the results are as follows:

1) The DDR frequency can be started normally after being changed to 3732MTS

2) The DDR frequency is changed to 4200MTS , it occasionally fails to start.However, the startup success rate is much higher than 4266MTS ;

Therefore, it can be inferred that the DDR frequency is too high, which makes tiboot3 unable to start normally on our custom TDA4 board.

My question is, if our board needs to be stable at 1066(ddr frequency ) or higher, how do we change or set it?Does the Jacinto7 DDRSS Register Configuration Tool need to set other parameters?

over 3 years ago

+1 Kevin S over 3 years ago

TI__Mastermind 38090 points

Hi,

A few thoughts:

If you haven't already, please make sure you have filled out the corresponding XLS of the following application note https://www.ti.com/lit/pdf/spracu8 , setting inputs to correspond to your custom system.
If still facing issues, can you try hand-editing your DTSI file with the changes described on this E2E post (and copied below)? https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1032456/tda4vm-the-program-run_app_multi_cam-sh-crashes-frequently-in-our-custom-tda4vm-board-using-sdk8-0-is-it-related-to-ddr-lp4-frequency/3818427?tisearch=e2e-sitesearch&keymatch=%252525252520user%25252525253A51195#3818427

For below registers, change the '7' to a '6' as shown below

#define DDRSS_PHY_33_DATA 0x0C002006
#define DDRSS_PHY_289_DATA 0x0C002006
#define DDRSS_PHY_545_DATA 0x0C002006
#define DDRSS_PHY_801_DATA 0x0C002006

For below registers, change the '20' to a '40' as shown below

#define DDRSS_PHY_32_DATA 0x10400000
#define DDRSS_PHY_288_DATA 0x10400000
#define DDRSS_PHY_544_DATA 0x10400000
#define DDRSS_PHY_800_DATA 0x10400000

Please let us know if still facing issues at LP4-4266 data rate after trying these suggestions.

Thanks,
Kevin

0 SandalHao over 3 years ago in reply to Kevin S

Intellectual 665 points

Hi,Kevin

Thank you for your answer.

We have designed two kind of boards,named type-A and type-B

After doing method 1, type-A can run DDR normally in 1066.5.

But type-B use method 1, method 2, or both methods, just still can't run DDR normally in 1066.5.Whether it is reduced to 933 or even 800, type-B still can't run. However, after switching tiboot3.bin back to 7.2 and the other three bootloader files are still 7.3, type-B can start normally.

I wonder why this change can solve type-A issue? How to solve the problem that type-B still can't run?

Thanks!

0 SandalHao over 3 years ago in reply to Kevin S

Intellectual 665 points

It seems that my problems can be divided into two categories. One can be solved by taking your suggestions. But the other kind can't. I'll re create a new ticket to explain. This ticket can be closed first now.

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TDA4VM: How to make DDR frequency operate normally at 4266MTS?