Hi Ti ,
I used this Zip packet: /cfs-file/__key/communityserver-discussions-components-files/791/7506.hlos.zip fromBrijesh Jadav, and verify boot flow is very nice.
I also refer to some descriptions of this ticket :https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1029452/tda4vm-how-to-boot-mcu-1-0-autosar-from-tiboot3/3809402#3809402 to compile binaries from ti-processor-sdk-rtos-j721e-evm-08_00_00_12 packet.
If used my app(combined.appimage) and all the other binaries are from /cfs-file/__key/communityserver-discussions-components-files/791/7506.hlos.zip , the u-boot-spl cannot transfer to u-boot scope.
Main domain UART log:
[12:28:16:9:25:296] NOTICE: BL31: Built : 16:34:52, Dec 20 2021
[12:28:16:9:25:296] ERROR: GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
[12:28:16:9:25:376]
[12:28:16:9:25:379] U-Boot SPL 2021.01-dirty (Dec 28 2021 - 15:41:57 +0800)
[12:28:16:9:25:379] Model: Texas Instruments K3 J721E SoC
[12:28:16:9:25:456] ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
[12:28:16:9:25:456] Board: J721EX-PM2-SOM rev E7
[12:28:16:9:25:456] SYSFW ABI: 3.1 (firmware rev 0x0015 '21.5.0--v2021.05 (Terrific Llam')
[12:28:16:9:25:552] probe_daughtercards: No daughtercard EEPROM at 0x52 found 1
[12:28:16:9:25:664] Detected: J7X-VSC8514-ETH rev E2
[12:28:16:9:25:664] Trying to boot from SPI
[12:28:16:9:25:792] Can't get reset: -2
[12:28:16:9:25:967] k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
[12:28:16:9:25:967] k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
So, my preliminary think that my u-boot-spl.bin is wrong.
My config.mk:
ATF_IMG ?= mpu1_0,$(HLOS_BIN_PATH)/bl31.bin,0x70000000,0x70000000
OPTEE_IMG ?= load_only,$(HLOS_BIN_PATH)/bl32.bin,0x9e800000,0x9e800000
#KERNEL_IMG ?= load_only,$(HLOS_BIN_PATH)/Image,0x80080000,0x80080000
# Use board-specific pre-built DTBs to ensure SD card filesystem is used for Linux boot
DTB_IMG ?= load_only,$(mkfile_dir)bin/$(BOARD)/base-board.dtb,0x82000000,0x82000000
#SPL_IMG ?= load_only,$(HLOS_BIN_PATH)/u-boot-spl.bin,0x80080000,0x80080000
SPL_IMG ?= load_only,$(HLOS_BIN_PATH)/../u-boot_build/a72/spl/u-boot-spl.bin,0x80080000,0x80080000
....
IMG1 ?= mcu1_0,XXXXX/ipc_echo_testb_tirtos/bin/j721e_evm/ipc_echo_testb_tirtos_mcu1_0_release_strip.xer5f
Now, I wonder, how should I compile u-boot-spl / u-boot ? Or do you need to change anything? why the u-boot.img is flashed 0x1500000 ?
Please help to check it.
BRs.
Thanks.
