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AM5706: DDR Throughput Difference betwen 16bit width and 32bit width

Hideaki Matsumoto
Expert 8570 points
Part Number: AM5706

Hi,

My customer has evaluated the DDR throughput performance of AM5706 with the following condition combinations.

  1. Core operation clock (1GHz / 800MHz / 600MHz / 400MHz)
  2. DDR Bus width (32bit / 16bit)
  3. Cache configurations (Enabled L1 cache and L2 cache / Enabled L1 cache only / Cache disabled)
  4. Consecutive access / Random access

As a result, The difference of throughput between 32bit and 16bit was just a few percent.

Do you think that this result is a reasonable outcome ?

Or the difference should be bigger ? If so, is there something wrong configuration on 16bit usage or 32bit usage ?

 

Best regards,
Hideaki

  • 0
    TI__Mastermind 32795 points

    Hi,

    I checked the following performance app note (which I believe should also apply to AM5706), but did not see any mention of 16-bit vs. 32-bit DDR performance. Thus, I'll have to check internally to see if this data exists.

    https://www.ti.com/lit/pdf/sprac46 

    However, I would assume a bigger difference between 32-bit and 16-bit IF the interface is being stressed to maximum throughput. For instance, a 400 MHz A15 clock may not be fast enough to stress the DDR interface if operating at DDR3-1066 data rate. At faster speeds,  cache operations may stress the interface,  but unless you can profile the cache operations specifically, there may be dead space in-between, giving the illusion that throughput is similar. 

    You might consider using EDMA to transfer large chunks of memory and profile only the EDMA transfer.

    Regarding the configuration, you should only need to toggle the NARROW_MODE bit field of the EMIF_SDRAM_CONFIG register. You can always probe the DQ signals with an oscilloscope to confirm 16-bit vs. 32-bit.

    Hope this helps,
    Kevin