Hello,
My colleagues and I are confused about what appears to be a dependency between DMA requests (DREQ) and interrupt requests (IRQ). Our specific use case is as follows:
- We are configuring AM5726 pin A10 as GPIO8_23.
- A rising edge on GPIO8 pin 23 is intended to trigger a DMA from DSP1, so we configure the PaRAM set for DSP1_EDMA channel 9 to perform the desired DMA transfer.
- We then set the DMA_DSP1_DREQ_9_IRQ_9 field of the CTRL_CORE_DMA_DSP1_DREQ_8_9 register to the value 194 (DMA_CROSSBAR_194 is GPIO8_DREQ_EVT).
This DMA transfer is working, but only when we ALSO enable rising-edge interrupt detection for GPIO8 pin 23, by setting bit 23 of the GPIO8 GPIO_RISINGDETECT register and bit 23 of the GPIO8 GPIO_IRQSTATUS_SET_0 register. If we do not set these bits, then the DMA does not occur. This is confusing to us because, as far as we can tell from the TRM, there is no relationship between DMA requests (DREQ) and interrupt requests (IRQ). So why should an IRQ need to be enabled for a DMA request to be serviced? We would prefer to not have to enable the rising-edge interrupt detection for GPIO8 pin 23.
Thanks in advance for your assistance, and best regards,
Dave