Hi sir,
I am Ramachandra ,
I am using Beagleboard-x15 with ti-processor-sdk-linux-am57xx-evm-06.01.00.08 and u-boot 2019.1 and Linux 4.19.59 using,
Actually Beagle board x-15 of p16 connector is connected our custom fpga board from fpga to rugged camera(1080p30) connected.(Beagle-->custom fpga(I2C3)-->camera)
From beagle board x15 we are able to communicating FPGA device through i2c3 and getting Device ID of FPGA.
Actually FPGA device i am taken like OV5640 device.
In DTS:
&vin3a {
vin3a_ep: endpoint {
remote-endpoint = <&cam>;
slave-mode;
};
};
&vip2 {
status = "okay";
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
ov5640@3C {
compatible = "ovti,ov5640";
reg = <0x3C>;
clock-names = "xclk";
clock-frequency = <24000000>;
port {
cam: endpoint {
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <1>;
remote-endpoint = <&vin3a_ep>;
};
};
};
};
OV5640 code some changes i have done:
/*
* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2014-2017 Mentor Graphics Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <media/v4l2-async.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
/* min/typical/max system clock (xclk) frequencies */
#define OV5640_XCLK_MIN 6000000
#define OV5640_XCLK_MAX 74250000
#define OV5640_DEFAULT_SLAVE_ID 0x3c
#define OV5640_REG_SYS_CARAVEL 0x3000
#define OV5640_REG_SYS_RESET02 0x3002
#define OV5640_REG_SYS_CLOCK_ENABLE02 0x3006
#define OV5640_REG_SYS_CTRL0 0x3008
#define OV5640_REG_CHIP_ID 0x300a
#define OV5640_REG_IO_MIPI_CTRL00 0x300e
#define OV5640_REG_PAD_OUTPUT_ENABLE01 0x3017
#define OV5640_REG_PAD_OUTPUT_ENABLE02 0x3018
#define OV5640_REG_PAD_OUTPUT00 0x3019
#define OV5640_REG_SYSTEM_CONTROL1 0x302e
#define OV5640_REG_SC_PLL_CTRL0 0x3034
#define OV5640_REG_SC_PLL_CTRL1 0x3035
#define OV5640_REG_SC_PLL_CTRL2 0x3036
#define OV5640_REG_SC_PLL_CTRL3 0x3037
#define OV5640_REG_SLAVE_ID 0x3100
#define OV5640_REG_SCCB_SYS_CTRL1 0x3103
#define OV5640_REG_SYS_ROOT_DIVIDER 0x3108
#define OV5640_REG_AWB_R_GAIN 0x3400
#define OV5640_REG_AWB_G_GAIN 0x3402
#define OV5640_REG_AWB_B_GAIN 0x3404
#define OV5640_REG_AWB_MANUAL_CTRL 0x3406
#define OV5640_REG_AEC_PK_EXPOSURE_HI 0x3500
#define OV5640_REG_AEC_PK_EXPOSURE_MED 0x3501
#define OV5640_REG_AEC_PK_EXPOSURE_LO 0x3502
#define OV5640_REG_AEC_PK_MANUAL 0x3503
#define OV5640_REG_AEC_PK_REAL_GAIN 0x350a
#define OV5640_REG_AEC_PK_VTS 0x350c
#define OV5640_REG_TIMING_DVPHO 0x3808
#define OV5640_REG_TIMING_DVPVO 0x380a
#define OV5640_REG_TIMING_HTS 0x380c
#define OV5640_REG_TIMING_VTS 0x380e
#define OV5640_REG_TIMING_TC_REG20 0x3820
#define OV5640_REG_TIMING_TC_REG21 0x3821
#define OV5640_REG_AEC_CTRL00 0x3a00
#define OV5640_REG_AEC_B50_STEP 0x3a08
#define OV5640_REG_AEC_B60_STEP 0x3a0a
#define OV5640_REG_AEC_CTRL0D 0x3a0d
#define OV5640_REG_AEC_CTRL0E 0x3a0e
#define OV5640_REG_AEC_CTRL0F 0x3a0f
#define OV5640_REG_AEC_CTRL10 0x3a10
#define OV5640_REG_AEC_CTRL11 0x3a11
#define OV5640_REG_AEC_CTRL1B 0x3a1b
#define OV5640_REG_AEC_CTRL1E 0x3a1e
#define OV5640_REG_AEC_CTRL1F 0x3a1f
#define OV5640_REG_HZ5060_CTRL00 0x3c00
#define OV5640_REG_HZ5060_CTRL01 0x3c01
#define OV5640_REG_SIGMADELTA_CTRL0C 0x3c0c
#define OV5640_REG_FRAME_CTRL01 0x4202
#define OV5640_REG_FORMAT_CONTROL00 0x4300
#define OV5640_REG_POLARITY_CTRL00 0x4740
#define OV5640_REG_MIPI_CTRL00 0x4800
#define OV5640_REG_DEBUG_MODE 0x4814
#define OV5640_REG_ISP_FORMAT_MUX_CTRL 0x501f
#define OV5640_REG_PRE_ISP_TEST_SET1 0x503d
#define OV5640_REG_SDE_CTRL0 0x5580
#define OV5640_REG_SDE_CTRL1 0x5581
#define OV5640_REG_SDE_CTRL3 0x5583
#define OV5640_REG_SDE_CTRL4 0x5584
#define OV5640_REG_SDE_CTRL5 0x5585
#define OV5640_REG_AVG_READOUT 0x56a1
enum ov5640_mode_id {
OV5640_MODE_QCIF_176_144 = 0,
OV5640_MODE_QVGA_320_240,
OV5640_MODE_VGA_640_480,
OV5640_MODE_NTSC_720_480,
OV5640_MODE_PAL_720_576,
OV5640_MODE_XGA_1024_768,
OV5640_MODE_720P_1280_720,
OV5640_MODE_1080P_1920_1080,
OV5640_MODE_QSXGA_2592_1944,
OV5640_NUM_MODES,
};
enum ov5640_frame_rate {
OV5640_15_FPS = 0,
OV5640_30_FPS,
OV5640_60_FPS,
OV5640_NUM_FRAMERATES,
};
struct ov5640_pixfmt {
u32 code;
u32 colorspace;
};
static const struct ov5640_pixfmt ov5640_formats[] = {
{ MEDIA_BUS_FMT_JPEG_1X8, V4L2_COLORSPACE_JPEG, },
{ MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB, },
{ MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB, },
{ MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB, },
{ MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB, },
};
/*
* FIXME: remove this when a subdev API becomes available
* to set the MIPI CSI-2 virtual channel.
*/
static unsigned int virtual_channel;
module_param(virtual_channel, uint, 0444);
MODULE_PARM_DESC(virtual_channel,
"MIPI CSI-2 virtual channel (0..3), default 0");
static const int ov5640_framerates[] = {
[OV5640_15_FPS] = 15,
[OV5640_30_FPS] = 30,
[OV5640_60_FPS] = 60,
};
/* regulator supplies */
static const char * const ov5640_supply_name[] = {
"DOVDD", /* Digital I/O (1.8V) supply */
"DVDD", /* Digital Core (1.5V) supply */
"AVDD", /* Analog (2.8V) supply */
};
#define OV5640_NUM_SUPPLIES ARRAY_SIZE(ov5640_supply_name)
/*
* Image size under 1280 * 960 are SUBSAMPLING
* Image size upper 1280 * 960 are SCALING
*/
enum ov5640_downsize_mode {
SUBSAMPLING,
SCALING,
};
struct reg_value {
u16 reg_addr;
u8 val;
u8 mask;
u32 delay_ms;
};
struct ov5640_mode_info {
enum ov5640_mode_id id;
enum ov5640_downsize_mode dn_mode;
u32 hact;
u32 htot;
u32 vact;
u32 vtot;
const struct reg_value *reg_data;
u32 reg_data_size;
};
struct ov5640_ctrls {
struct v4l2_ctrl_handler handler;
struct {
struct v4l2_ctrl *pixel_rate;
};
struct {
struct v4l2_ctrl *auto_exp;
struct v4l2_ctrl *exposure;
};
struct {
struct v4l2_ctrl *auto_wb;
struct v4l2_ctrl *blue_balance;
struct v4l2_ctrl *red_balance;
};
struct {
struct v4l2_ctrl *auto_gain;
struct v4l2_ctrl *gain;
};
struct v4l2_ctrl *brightness;
struct v4l2_ctrl *light_freq;
struct v4l2_ctrl *saturation;
struct v4l2_ctrl *contrast;
struct v4l2_ctrl *hue;
struct v4l2_ctrl *test_pattern;
struct v4l2_ctrl *hflip;
struct v4l2_ctrl *vflip;
};
struct ov5640_dev {
struct i2c_client *i2c_client;
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
struct clk *xclk; /* system clock to OV5640 */
u32 xclk_freq;
struct regulator_bulk_data supplies[OV5640_NUM_SUPPLIES];
struct gpio_desc *reset_gpio;
struct gpio_desc *pwdn_gpio;
bool upside_down;
/* lock to protect all members below */
struct mutex lock;
int power_count;
struct v4l2_mbus_framefmt fmt;
bool pending_fmt_change;
const struct ov5640_mode_info *current_mode;
const struct ov5640_mode_info *last_mode;
enum ov5640_frame_rate current_fr;
struct v4l2_fract frame_interval;
u64 pixel_rate;
struct ov5640_ctrls ctrls;
u32 prev_sysclk, prev_hts;
u32 ae_low, ae_high, ae_target;
bool pending_mode_change;
bool streaming;
};
static inline struct ov5640_dev *to_ov5640_dev(struct v4l2_subdev *sd)
{
return container_of(sd, struct ov5640_dev, sd);
}
static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
{
return &container_of(ctrl->handler, struct ov5640_dev,
ctrls.handler)->sd;
}
/*
* FIXME: all of these register tables are likely filled with
* entries that set the register to their power-on default values,
* and which are otherwise not touched by this driver. Those entries
* should be identified and removed to speed register load time
* over i2c.
*/
/* YUV422 UYVY VGA@30fps */
static const struct reg_value ov5640_init_setting_30fps_VGA[] = {
{0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0},
{0x3103, 0x03, 0, 0}, {0x3017, 0x00, 0, 0}, {0x3018, 0x00, 0, 0},
{0x3630, 0x36, 0, 0},
{0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
{0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
{0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
{0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
{0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
{0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
{0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
{0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
{0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
{0x3c01, 0xa4, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
{0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
{0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
{0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0},
{0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
{0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x4837, 0x0a, 0, 0}, {0x3824, 0x02, 0, 0},
{0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0},
{0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0},
{0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0},
{0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0},
{0x518a, 0x54, 0, 0}, {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0},
{0x518d, 0x50, 0, 0}, {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0},
{0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0},
{0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0},
{0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0},
{0x5199, 0x6c, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0},
{0x519c, 0x09, 0, 0}, {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0},
{0x5381, 0x1e, 0, 0}, {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0},
{0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0},
{0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0},
{0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0},
{0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0},
{0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0},
{0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0},
{0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0},
{0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0},
{0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0},
{0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0},
{0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0},
{0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0},
{0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0},
{0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0},
{0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0},
{0x5802, 0x0f, 0, 0}, {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0},
{0x5805, 0x26, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0},
{0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0},
{0x580b, 0x0d, 0, 0}, {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0},
{0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0},
{0x5811, 0x09, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0},
{0x5814, 0x00, 0, 0}, {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0},
{0x5817, 0x08, 0, 0}, {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0},
{0x581a, 0x05, 0, 0}, {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0},
{0x581d, 0x0e, 0, 0}, {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0},
{0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0},
{0x5823, 0x28, 0, 0}, {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0},
{0x5826, 0x08, 0, 0}, {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0},
{0x5829, 0x26, 0, 0}, {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0},
{0x582c, 0x24, 0, 0}, {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0},
{0x582f, 0x22, 0, 0}, {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0},
{0x5832, 0x24, 0, 0}, {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0},
{0x5835, 0x22, 0, 0}, {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0},
{0x5838, 0x44, 0, 0}, {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0},
{0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0},
{0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0},
{0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0},
{0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300},
};
static const struct reg_value ov5640_setting_VGA_640_480[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
static const struct reg_value ov5640_setting_XGA_1024_768[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
static const struct reg_value ov5640_setting_QVGA_320_240[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
static const struct reg_value ov5640_setting_QCIF_176_144[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
static const struct reg_value ov5640_setting_NTSC_720_480[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
static const struct reg_value ov5640_setting_PAL_720_576[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
static const struct reg_value ov5640_setting_720P_1280_720[] = {
{0x3c07, 0x07, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x31, 0, 0},
{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
{0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
{0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
{0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
{0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
};
static const struct reg_value ov5640_setting_1080P_1920_1080[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x11, 0, 0},
{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
{0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0},
{0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
{0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
{0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0},
{0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
{0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
{0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
{0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
{0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
{0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
{0x4005, 0x1a, 0, 0},
};
static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
{0x3814, 0x11, 0, 0},
{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
{0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
{0x3810, 0x00, 0, 0},
{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
{0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70},
};
/* power-on sensor init reg table */
static const struct ov5640_mode_info ov5640_mode_init_data = {
0, SUBSAMPLING, 640, 1896, 480, 984,
ov5640_init_setting_30fps_VGA,
ARRAY_SIZE(ov5640_init_setting_30fps_VGA),
};
static const struct ov5640_mode_info
ov5640_mode_data[OV5640_NUM_MODES] = {
{OV5640_MODE_QCIF_176_144, SUBSAMPLING,
176, 1896, 144, 984,
ov5640_setting_QCIF_176_144,
ARRAY_SIZE(ov5640_setting_QCIF_176_144)},
{OV5640_MODE_QVGA_320_240, SUBSAMPLING,
320, 1896, 240, 984,
ov5640_setting_QVGA_320_240,
ARRAY_SIZE(ov5640_setting_QVGA_320_240)},
{OV5640_MODE_VGA_640_480, SUBSAMPLING,
640, 1896, 480, 1080,
ov5640_setting_VGA_640_480,
ARRAY_SIZE(ov5640_setting_VGA_640_480)},
{OV5640_MODE_NTSC_720_480, SUBSAMPLING,
720, 1896, 480, 984,
ov5640_setting_NTSC_720_480,
ARRAY_SIZE(ov5640_setting_NTSC_720_480)},
{OV5640_MODE_PAL_720_576, SUBSAMPLING,
720, 1896, 576, 984,
ov5640_setting_PAL_720_576,
ARRAY_SIZE(ov5640_setting_PAL_720_576)},
{OV5640_MODE_XGA_1024_768, SUBSAMPLING,
1024, 1896, 768, 1080,
ov5640_setting_XGA_1024_768,
ARRAY_SIZE(ov5640_setting_XGA_1024_768)},
{OV5640_MODE_720P_1280_720, SUBSAMPLING,
1280, 1892, 720, 740,
ov5640_setting_720P_1280_720,
ARRAY_SIZE(ov5640_setting_720P_1280_720)},
{OV5640_MODE_1080P_1920_1080, SCALING,
1920, 2500, 1080, 1120,
ov5640_setting_1080P_1920_1080,
ARRAY_SIZE(ov5640_setting_1080P_1920_1080)},
{OV5640_MODE_QSXGA_2592_1944, SCALING,
2592, 2844, 1944, 1968,
ov5640_setting_QSXGA_2592_1944,
ARRAY_SIZE(ov5640_setting_QSXGA_2592_1944)},
};
static int ov5640_init_slave_id(struct ov5640_dev *sensor)
{
struct i2c_client *client = sensor->i2c_client;
struct i2c_msg msg;
u8 buf[3];
int ret;
dev_err(&client->dev, "%s: client->addr= %x\n", __func__,client->addr );
if (client->addr == OV5640_DEFAULT_SLAVE_ID)
return 0;
buf[0] = OV5640_REG_SLAVE_ID >> 8;
buf[1] = OV5640_REG_SLAVE_ID & 0xff;
buf[2] = client->addr << 1;
msg.addr = OV5640_DEFAULT_SLAVE_ID;
msg.flags = 0;
msg.buf = buf;
msg.len = sizeof(buf);
ret = i2c_transfer(client->adapter, &msg, 1);
if (ret < 0) {
dev_err(&client->dev, "%s: failed with %d\n", __func__, ret);
return ret;
}
return 0;
}
static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
{
struct i2c_client *client = sensor->i2c_client;
struct i2c_msg msg;
u8 buf[3];
int ret;
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
buf[2] = val;
msg.addr = client->addr;
msg.flags = client->flags;
msg.buf = buf;
msg.len = sizeof(buf);
ret = i2c_transfer(client->adapter, &msg, 1);
if (ret < 0) {
dev_err(&client->dev, "%s: error: reg=%x, val=%x\n",
__func__, reg, val);
return ret;
}
return 0;
}
static int ov5640_cispl_read_reg(struct ov5640_dev *sensor, u16 reg, u16 *val)
{
struct i2c_client *client = sensor->i2c_client;
struct i2c_msg msg[1];
u8 buf[2];
int ret;
buf[0] = reg & 0xff;
msg[0].addr = client->addr;
msg[0].flags = client->flags | I2C_M_RD;
msg[0].buf = buf;
msg[0].len = 2;
ret = i2c_transfer(client->adapter, msg, 1);
if (ret < 0) {
dev_err(&client->dev, "%s: error: reg=%x\n",
__func__, reg);
return ret;
}
*val = buf[0]<<8 | buf[1];;
// *val = buf[0];
return 0;
}
static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val)
{
struct i2c_client *client = sensor->i2c_client;
struct i2c_msg msg[2];
u8 buf[2];
int ret;
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
msg[0].addr = client->addr;
msg[0].flags = client->flags;
msg[0].buf = buf;
msg[0].len = sizeof(buf);
msg[1].addr = client->addr;
msg[1].flags = client->flags | I2C_M_RD;
msg[1].buf = buf;
msg[1].len = 1;
ret = i2c_transfer(client->adapter, msg, 2);
if (ret < 0) {
dev_err(&client->dev, "%s: error: reg=%x\n",
__func__, reg);
return ret;
}
*val = buf[0];
return 0;
}
static int ov5640_read_reg16(struct ov5640_dev *sensor, u16 reg, u16 *val)
{
u8 hi, lo;
int ret;
ret = ov5640_read_reg(sensor, reg, &hi);
if (ret)
return ret;
ret = ov5640_read_reg(sensor, reg + 1, &lo);
if (ret)
return ret;
*val = ((u16)hi << 8) | (u16)lo;
return 0;
}
static int ov5640_write_reg16(struct ov5640_dev *sensor, u16 reg, u16 val)
{
int ret;
ret = ov5640_write_reg(sensor, reg, val >> 8);
if (ret)
return ret;
return ov5640_write_reg(sensor, reg + 1, val & 0xff);
}
static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg,
u8 mask, u8 val)
{
u8 readval;
int ret;
ret = ov5640_read_reg(sensor, reg, &readval);
if (ret)
return ret;
readval &= ~mask;
val &= mask;
val |= readval;
return ov5640_write_reg(sensor, reg, val);
}
/*
* After trying the various combinations, reading various
* documentations spreaded around the net, and from the various
* feedback, the clock tree is probably as follows:
*
* +--------------+
* | Ext. Clock |
* +-+------------+
* | +----------+
* +->| PLL1 | - reg 0x3036, for the multiplier
* +-+--------+ - reg 0x3037, bits 0-3 for the pre-divider
* | +--------------+
* +->| System Clock | - reg 0x3035, bits 4-7
* +-+------------+
* | +--------------+
* +->| MIPI Divider | - reg 0x3035, bits 0-3
* | +-+------------+
* | +----------------> MIPI SCLK
* | + +-----+
* | +->| / 2 |-------> MIPI BIT CLK
* | +-----+
* | +--------------+
* +->| PLL Root Div | - reg 0x3037, bit 4
* +-+------------+
* | +---------+
* +->| Bit Div | - reg 0x3035, bits 0-3
* +-+-------+
* | +-------------+
* +->| SCLK Div | - reg 0x3108, bits 0-1
* | +-+-----------+
* | +---------------> SCLK
* | +-------------+
* +->| SCLK 2X Div | - reg 0x3108, bits 2-3
* | +-+-----------+
* | +---------------> SCLK 2X
* | +-------------+
* +->| PCLK Div | - reg 0x3108, bits 4-5
* ++------------+
* + +-----------+
* +->| P_DIV | - reg 0x3035, bits 0-3
* +-----+-----+
* +------------> PCLK
*
* This is deviating from the datasheet at least for the register
* 0x3108, since it's said here that the PCLK would be clocked from
* the PLL.
*
* There seems to be also (unverified) constraints:
* - the PLL pre-divider output rate should be in the 4-27MHz range
* - the PLL multiplier output rate should be in the 500-1000MHz range
* - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG
*
* In the two latter cases, these constraints are met since our
* factors are hardcoded. If we were to change that, we would need to
* take this into account. The only varying parts are the PLL
* multiplier and the system clock divider, which are shared between
* all these clocks so won't cause any issue.
*/
/*
* This is supposed to be ranging from 1 to 8, but the value is always
* set to 3 in the vendor kernels.
*/
#define OV5640_PLL_PREDIV 3
#define OV5640_PLL_MULT_MIN 4
#define OV5640_PLL_MULT_MAX 252
/*
* This is supposed to be ranging from 1 to 16, but the value is
* always set to either 1 or 2 in the vendor kernels.
*/
#define OV5640_SYSDIV_MIN 1
#define OV5640_SYSDIV_MAX 16
/*
* Hardcode these values for scaler and non-scaler modes.
* FIXME: to be re-calcualted for 1 data lanes setups
*/
#define OV5640_MIPI_DIV_PCLK 2
#define OV5640_MIPI_DIV_SCLK 1
/*
* This is supposed to be ranging from 1 to 2, but the value is always
* set to 2 in the vendor kernels.
*/
#define OV5640_PLL_ROOT_DIV 2
#define OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 BIT(4)
/*
* We only supports 8-bit formats at the moment
*/
#define OV5640_BIT_DIV 2
#define OV5640_PLL_CTRL0_MIPI_MODE_8BIT 0x08
/*
* This is supposed to be ranging from 1 to 8, but the value is always
* set to 2 in the vendor kernels.
*/
#define OV5640_SCLK_ROOT_DIV 2
/*
* This is hardcoded so that the consistency is maintained between SCLK and
* SCLK 2x.
*/
#define OV5640_SCLK2X_ROOT_DIV (OV5640_SCLK_ROOT_DIV / 2)
/*
* This is supposed to be ranging from 1 to 8, but the value is always
* set to 1 in the vendor kernels.
*/
#define OV5640_PCLK_ROOT_DIV 1
#define OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS 0x00
static unsigned long ov5640_compute_sys_clk(struct ov5640_dev *sensor,
u8 pll_prediv, u8 pll_mult,
u8 sysdiv)
{
unsigned long sysclk = sensor->xclk_freq / pll_prediv * pll_mult;
/* PLL1 output cannot exceed 1GHz. */
if (sysclk / 1000000 > 1000)
return 0;
return sysclk / sysdiv;
}
static unsigned long ov5640_calc_sys_clk(struct ov5640_dev *sensor,
unsigned long rate,
u8 *pll_prediv, u8 *pll_mult,
u8 *sysdiv)
{
unsigned long best = ~0;
u8 best_sysdiv = 1, best_mult = 1;
u8 _sysdiv, _pll_mult;
for (_sysdiv = OV5640_SYSDIV_MIN;
_sysdiv <= OV5640_SYSDIV_MAX;
_sysdiv++) {
for (_pll_mult = OV5640_PLL_MULT_MIN;
_pll_mult <= OV5640_PLL_MULT_MAX;
_pll_mult++) {
unsigned long _rate;
/*
* The PLL multiplier cannot be odd if above
* 127.
*/
if (_pll_mult > 127 && (_pll_mult % 2))
continue;
_rate = ov5640_compute_sys_clk(sensor,
OV5640_PLL_PREDIV,
_pll_mult, _sysdiv);
/*
* We have reached the maximum allowed PLL1 output,
* increase sysdiv.
*/
if (!rate)
break;
/*
* Prefer rates above the expected clock rate than
* below, even if that means being less precise.
*/
if (_rate < rate)
continue;
if (abs(rate - _rate) < abs(rate - best)) {
best = _rate;
best_sysdiv = _sysdiv;
best_mult = _pll_mult;
}
if (_rate == rate)
goto out;
}
}
out:
*sysdiv = best_sysdiv;
*pll_prediv = OV5640_PLL_PREDIV;
*pll_mult = best_mult;
return best;
}
/*
* ov5640_set_mipi_pclk() - Calculate the clock tree configuration values
* for the MIPI CSI-2 output.
*
* @rate: The requested bandwidth per lane in bytes per second.
* 'Bandwidth Per Lane' is calculated as:
* bpl = HTOT * VTOT * FPS * bpp / num_lanes;
*
* This function use the requested bandwidth to calculate:
* - sample_rate = bpl / (bpp / num_lanes);
* = bpl / (PLL_RDIV * BIT_DIV * PCLK_DIV * MIPI_DIV / num_lanes);
*
* - mipi_sclk = bpl / MIPI_DIV / 2; ( / 2 is for CSI-2 DDR)
*
* with these fixed parameters:
* PLL_RDIV = 2;
* BIT_DIVIDER = 2; (MIPI_BIT_MODE == 8 ? 2 : 2,5);
* PCLK_DIV = 1;
*
* The MIPI clock generation differs for modes that use the scaler and modes
* that do not. In case the scaler is in use, the MIPI_SCLK generates the MIPI
* BIT CLk, and thus:
*
* - mipi_sclk = bpl / MIPI_DIV / 2;
* MIPI_DIV = 1;
*
* For modes that do not go through the scaler, the MIPI BIT CLOCK is generated
* from the pixel clock, and thus:
*
* - sample_rate = bpl / (bpp / num_lanes);
* = bpl / (2 * 2 * 1 * MIPI_DIV / num_lanes);
* = bpl / (4 * MIPI_DIV / num_lanes);
* - MIPI_DIV = bpp / (4 * num_lanes);
*
* FIXME: this have been tested with 16bpp and 2 lanes setup only.
* MIPI_DIV is fixed to value 2, but it -might- be changed according to the
* above formula for setups with 1 lane or image formats with different bpp.
*
* FIXME: this deviates from the sensor manual documentation which is quite
* thin on the MIPI clock tree generation part.
*/
static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor,
unsigned long rate)
{
const struct ov5640_mode_info *mode = sensor->current_mode;
u8 prediv, mult, sysdiv;
u8 mipi_div;
int ret;
/*
* 1280x720 is reported to use 'SUBSAMPLING' only,
* but according to the sensor manual it goes through the
* scaler before subsampling.
*/
if (mode->dn_mode == SCALING ||
(mode->id == OV5640_MODE_720P_1280_720))
mipi_div = OV5640_MIPI_DIV_SCLK;
else
mipi_div = OV5640_MIPI_DIV_PCLK;
ov5640_calc_sys_clk(sensor, rate, &prediv, &mult, &sysdiv);
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
0x0f, OV5640_PLL_CTRL0_MIPI_MODE_8BIT);
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
0xff, sysdiv << 4 | mipi_div);
if (ret)
return ret;
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2, 0xff, mult);
if (ret)
return ret;
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
0x1f, OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 | prediv);
if (ret)
return ret;
return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER,
0x30, OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS);
}
static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor,
unsigned long rate,
u8 *pll_prediv, u8 *pll_mult, u8 *sysdiv,
u8 *pll_rdiv, u8 *bit_div, u8 *pclk_div)
{
unsigned long _rate = rate * OV5640_PLL_ROOT_DIV * OV5640_BIT_DIV *
OV5640_PCLK_ROOT_DIV;
_rate = ov5640_calc_sys_clk(sensor, _rate, pll_prediv, pll_mult,
sysdiv);
*pll_rdiv = OV5640_PLL_ROOT_DIV;
*bit_div = OV5640_BIT_DIV;
*pclk_div = OV5640_PCLK_ROOT_DIV;
return _rate / *pll_rdiv / *bit_div / *pclk_div;
}
static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, unsigned long rate)
{
u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div;
int ret;
ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv,
&bit_div, &pclk_div);
if (bit_div == 2)
bit_div = 8;
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
0x0f, bit_div);
if (ret)
return ret;
/*
* We need to set sysdiv according to the clock, and to clear
* the MIPI divider.
*/
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
0xff, sysdiv << 4);
if (ret)
return ret;
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2,
0xff, mult);
if (ret)
return ret;
ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
0x1f, prediv | ((pll_rdiv - 1) << 4));
if (ret)
return ret;
return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x30,
(ilog2(pclk_div) << 4));
}
/* download ov5640 settings to sensor through i2c */
static int ov5640_set_timings(struct ov5640_dev *sensor,
const struct ov5640_mode_info *mode)
{
int ret;
ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPHO, mode->hact);
if (ret < 0)
return ret;
ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPVO, mode->vact);
if (ret < 0)
return ret;
ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_HTS, mode->htot);
if (ret < 0)
return ret;
return ov5640_write_reg16(sensor, OV5640_REG_TIMING_VTS, mode->vtot);
}
static int ov5640_load_regs(struct ov5640_dev *sensor,
const struct ov5640_mode_info *mode)
{
const struct reg_value *regs = mode->reg_data;
unsigned int i;
u32 delay_ms;
u16 reg_addr;
u8 mask, val;
int ret = 0;
for (i = 0; i < mode->reg_data_size; ++i, ++regs) {
delay_ms = regs->delay_ms;
reg_addr = regs->reg_addr;
val = regs->val;
mask = regs->mask;
if (mask)
ret = ov5640_mod_reg(sensor, reg_addr, mask, val);
else
ret = ov5640_write_reg(sensor, reg_addr, val);
if (ret)
break;
if (delay_ms)
usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
}
return ov5640_set_timings(sensor, mode);
}
static int ov5640_set_autoexposure(struct ov5640_dev *sensor, bool on)
{
return ov5640_mod_reg(sensor, OV5640_REG_AEC_PK_MANUAL,
BIT(0), on ? 0 : BIT(0));
}
/* read exposure, in number of line periods */
static int ov5640_get_exposure(struct ov5640_dev *sensor)
{
int exp, ret;
u8 temp;
ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_HI, &temp);
if (ret)
return ret;
exp = ((int)temp & 0x0f) << 16;
ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_MED, &temp);
if (ret)
return ret;
exp |= ((int)temp << 8);
ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_LO, &temp);
if (ret)
return ret;
exp |= (int)temp;
return exp >> 4;
}
/* write exposure, given number of line periods */
static int ov5640_set_exposure(struct ov5640_dev *sensor, u32 exposure)
{
int ret;
exposure <<= 4;
ret = ov5640_write_reg(sensor,
OV5640_REG_AEC_PK_EXPOSURE_LO,
exposure & 0xff);
if (ret)
return ret;
ret = ov5640_write_reg(sensor,
OV5640_REG_AEC_PK_EXPOSURE_MED,
(exposure >> 8) & 0xff);
if (ret)
return ret;
return ov5640_write_reg(sensor,
OV5640_REG_AEC_PK_EXPOSURE_HI,
(exposure >> 16) & 0x0f);
}
static int ov5640_get_gain(struct ov5640_dev *sensor)
{
u16 gain;
int ret;
ret = ov5640_read_reg16(sensor, OV5640_REG_AEC_PK_REAL_GAIN, &gain);
if (ret)
return ret;
return gain & 0x3ff;
}
static int ov5640_set_gain(struct ov5640_dev *sensor, int gain)
{
return ov5640_write_reg16(sensor, OV5640_REG_AEC_PK_REAL_GAIN,
(u16)gain & 0x3ff);
}
static int ov5640_set_autogain(struct ov5640_dev *sensor, bool on)
{
return ov5640_mod_reg(sensor, OV5640_REG_AEC_PK_MANUAL,
BIT(1), on ? 0 : BIT(1));
}
static int ov5640_set_stream_dvp(struct ov5640_dev *sensor, bool on)
{
int ret;
unsigned int flags = sensor->ep.bus.parallel.flags;
u8 pclk_pol = 0;
u8 hsync_pol = 0;
u8 vsync_pol = 0;
/*
* Note about parallel port configuration.
*
* When configured in parallel mode, the OV5640 will
* output 10 bits data on DVP data lines [9:0].
* If only 8 bits data are wanted, the 8 bits data lines
* of the camera interface must be physically connected
* on the DVP data lines [9:2].
*
* Control lines polarity can be configured through
* devicetree endpoint control lines properties.
* If no endpoint control lines properties are set,
* polarity will be as below:
* - VSYNC: active high
* - HREF: active low
* - PCLK: active low
*/
if (on) {
/*
* configure parallel port control lines polarity
*
* POLARITY CTRL0
* - [5]: PCLK polarity (0: active low, 1: active high)
* - [1]: HREF polarity (0: active low, 1: active high)
* - [0]: VSYNC polarity (mismatch here between
* datasheet and hardware, 0 is active high
* and 1 is active low...)
*/
if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
pclk_pol = 1;
if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
hsync_pol = 1;
if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
vsync_pol = 1;
ret = ov5640_write_reg(sensor,
OV5640_REG_POLARITY_CTRL00,
(pclk_pol << 5) |
(hsync_pol << 1) |
vsync_pol);
if (ret)
return ret;
}
/*
* powerdown MIPI TX/RX PHY & disable MIPI
*
* MIPI CONTROL 00
* 4: PWDN PHY TX
* 3: PWDN PHY RX
* 2: MIPI enable
*/
ret = ov5640_write_reg(sensor,
OV5640_REG_IO_MIPI_CTRL00, on ? 0x18 : 0);
if (ret)
return ret;
/*
* enable VSYNC/HREF/PCLK DVP control lines
* & D[9:6] DVP data lines
*
* PAD OUTPUT ENABLE 01
* - 6: VSYNC output enable
* - 5: HREF output enable
* - 4: PCLK output enable
* - [3:0]: D[9:6] output enable
*/
ret = ov5640_write_reg(sensor,
OV5640_REG_PAD_OUTPUT_ENABLE01,
on ? 0x7f : 0);
if (ret)
return ret;
/*
* enable D[5:0] DVP data lines
*
* PAD OUTPUT ENABLE 02
* - [7:2]: D[5:0] output enable
*/
return ov5640_write_reg(sensor,
OV5640_REG_PAD_OUTPUT_ENABLE02,
on ? 0xfc : 0);
}
static int ov5640_set_stream_mipi(struct ov5640_dev *sensor, bool on)
{
int ret;
/*
* Enable/disable the MIPI interface
*
* 0x300e = on ? 0x45 : 0x40
*
* FIXME: the sensor manual (version 2.03) reports
* [7:5] = 000 : 1 data lane mode
* [7:5] = 001 : 2 data lanes mode
* But this settings do not work, while the following ones
* have been validated for 2 data lanes mode.
*
* [7:5] = 010 : 2 data lanes mode
* [4] = 0 : Power up MIPI HS Tx
* [3] = 0 : Power up MIPI LS Rx
* [2] = 1/0 : MIPI interface enable/disable
* [1:0] = 01/00: FIXME: 'debug'
*/
ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00,
on ? 0x45 : 0x40);
if (ret)
return ret;
return ov5640_write_reg(sensor, OV5640_REG_FRAME_CTRL01,
on ? 0x00 : 0x0f);
}
static int ov5640_get_sysclk(struct ov5640_dev *sensor)
{
/* calculate sysclk */
u32 xvclk = sensor->xclk_freq / 10000;
u32 multiplier, prediv, VCO, sysdiv, pll_rdiv;
u32 sclk_rdiv_map[] = {1, 2, 4, 8};
u32 bit_div2x = 1, sclk_rdiv, sysclk;
u8 temp1, temp2;
int ret;
ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL0, &temp1);
if (ret)
return ret;
temp2 = temp1 & 0x0f;
if (temp2 == 8 || temp2 == 10)
bit_div2x = temp2 / 2;
ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL1, &temp1);
if (ret)
return ret;
sysdiv = temp1 >> 4;
if (sysdiv == 0)
sysdiv = 16;
ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL2, &temp1);
if (ret)
return ret;
multiplier = temp1;
ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL3, &temp1);
if (ret)
return ret;
prediv = temp1 & 0x0f;
pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
ret = ov5640_read_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, &temp1);
if (ret)
return ret;
temp2 = temp1 & 0x03;
sclk_rdiv = sclk_rdiv_map[temp2];
if (!prediv || !sysdiv || !pll_rdiv || !bit_div2x)
return -EINVAL;
VCO = xvclk * multiplier / prediv;
sysclk = VCO / sysdiv / pll_rdiv * 2 / bit_div2x / sclk_rdiv;
return sysclk;
}
static int ov5640_set_night_mode(struct ov5640_dev *sensor)
{
/* read HTS from register settings */
u8 mode;
int ret;
ret = ov5640_read_reg(sensor, OV5640_REG_AEC_CTRL00, &mode);
if (ret)
return ret;
mode &= 0xfb;
return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL00, mode);
}
static int ov5640_get_hts(struct ov5640_dev *sensor)
{
/* read HTS from register settings */
u16 hts;
int ret;
ret = ov5640_read_reg16(sensor, OV5640_REG_TIMING_HTS, &hts);
if (ret)
return ret;
return hts;
}
static int ov5640_get_vts(struct ov5640_dev *sensor)
{
u16 vts;
int ret;
ret = ov5640_read_reg16(sensor, OV5640_REG_TIMING_VTS, &vts);
if (ret)
return ret;
return vts;
}
static int ov5640_set_vts(struct ov5640_dev *sensor, int vts)
{
return ov5640_write_reg16(sensor, OV5640_REG_TIMING_VTS, vts);
}
static int ov5640_get_light_freq(struct ov5640_dev *sensor)
{
/* get banding filter value */
int ret, light_freq = 0;
u8 temp, temp1;
ret = ov5640_read_reg(sensor, OV5640_REG_HZ5060_CTRL01, &temp);
if (ret)
return ret;
if (temp & 0x80) {
/* manual */
ret = ov5640_read_reg(sensor, OV5640_REG_HZ5060_CTRL00,
&temp1);
if (ret)
return ret;
if (temp1 & 0x04) {
/* 50Hz */
light_freq = 50;
} else {
/* 60Hz */
light_freq = 60;
}
} else {
/* auto */
ret = ov5640_read_reg(sensor, OV5640_REG_SIGMADELTA_CTRL0C,
&temp1);
if (ret)
return ret;
if (temp1 & 0x01) {
/* 50Hz */
light_freq = 50;
} else {
/* 60Hz */
}
}
return light_freq;
}
static int ov5640_set_bandingfilter(struct ov5640_dev *sensor)
{
u32 band_step60, max_band60, band_step50, max_band50, prev_vts;
int ret;
/* read preview PCLK */
ret = ov5640_get_sysclk(sensor);
if (ret < 0)
return ret;
if (ret == 0)
return -EINVAL;
sensor->prev_sysclk = ret;
/* read preview HTS */
ret = ov5640_get_hts(sensor);
if (ret < 0)
return ret;
if (ret == 0)
return -EINVAL;
sensor->prev_hts = ret;
/* read preview VTS */
ret = ov5640_get_vts(sensor);
if (ret < 0)
return ret;
prev_vts = ret;
/* calculate banding filter */
/* 60Hz */
band_step60 = sensor->prev_sysclk * 100 / sensor->prev_hts * 100 / 120;
ret = ov5640_write_reg16(sensor, OV5640_REG_AEC_B60_STEP, band_step60);
if (ret)
return ret;
if (!band_step60)
return -EINVAL;
max_band60 = (int)((prev_vts - 4) / band_step60);
ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0D, max_band60);
if (ret)
return ret;
/* 50Hz */
band_step50 = sensor->prev_sysclk * 100 / sensor->prev_hts;
ret = ov5640_write_reg16(sensor, OV5640_REG_AEC_B50_STEP, band_step50);
if (ret)
return ret;
if (!band_step50)
return -EINVAL;
max_band50 = (int)((prev_vts - 4) / band_step50);
return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0E, max_band50);
}
static int ov5640_set_ae_target(struct ov5640_dev *sensor, int target)
{
/* stable in high */
u32 fast_high, fast_low;
int ret;
sensor->ae_low = target * 23 / 25; /* 0.92 */
sensor->ae_high = target * 27 / 25; /* 1.08 */
fast_high = sensor->ae_high << 1;
if (fast_high > 255)
fast_high = 255;
fast_low = sensor->ae_low >> 1;
ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0F, sensor->ae_high);
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL10, sensor->ae_low);
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1B, sensor->ae_high);
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1E, sensor->ae_low);
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL11, fast_high);
if (ret)
return ret;
return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1F, fast_low);
}
static int ov5640_get_binning(struct ov5640_dev *sensor)
{
u8 temp;
int ret;
ret = ov5640_read_reg(sensor, OV5640_REG_TIMING_TC_REG21, &temp);
if (ret)
return ret;
return temp & BIT(0);
}
static int ov5640_set_binning(struct ov5640_dev *sensor, bool enable)
{
int ret;
/*
* TIMING TC REG21:
* - [0]: Horizontal binning enable
*/
ret = ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
BIT(0), enable ? BIT(0) : 0);
if (ret)
return ret;
/*
* TIMING TC REG20:
* - [0]: Undocumented, but hardcoded init sequences
* are always setting REG21/REG20 bit 0 to same value...
*/
return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG20,
BIT(0), enable ? BIT(0) : 0);
}
static int ov5640_set_virtual_channel(struct ov5640_dev *sensor)
{
struct i2c_client *client = sensor->i2c_client;
u8 temp, channel = virtual_channel;
int ret;
if (channel > 3) {
dev_err(&client->dev,
"%s: wrong virtual_channel parameter, expected (0..3), got %d\n",
__func__, channel);
return -EINVAL;
}
ret = ov5640_read_reg(sensor, OV5640_REG_DEBUG_MODE, &temp);
if (ret)
return ret;
temp &= ~(3 << 6);
temp |= (channel << 6);
return ov5640_write_reg(sensor, OV5640_REG_DEBUG_MODE, temp);
}
static const struct ov5640_mode_info *
ov5640_find_mode(struct ov5640_dev *sensor, enum ov5640_frame_rate fr,
int width, int height, bool nearest)
{
const struct ov5640_mode_info *mode;
mode = v4l2_find_nearest_size(ov5640_mode_data,
ARRAY_SIZE(ov5640_mode_data),
hact, vact,
width, height);
if (!mode ||
(!nearest && (mode->hact != width || mode->vact != height)))
return NULL;
/* Only 640x480 can operate at 60fps (for now) */
if (fr == OV5640_60_FPS &&
!(mode->hact == 640 && mode->vact == 480))
return NULL;
if (fr == OV5640_30_FPS &&
!(mode->hact == 1920 && mode->vact == 1080))
return NULL;
/* 2592x1944 only works at 15fps */
if (fr != OV5640_15_FPS &&
(mode->hact == 2592 && mode->vact == 1944))
return NULL;
return mode;
}
/*
* sensor changes between scaling and subsampling, go through
* exposure calculation
*/
static int ov5640_set_mode_exposure_calc(struct ov5640_dev *sensor,
const struct ov5640_mode_info *mode)
{
u32 prev_shutter, prev_gain16;
u32 cap_shutter, cap_gain16;
u32 cap_sysclk, cap_hts, cap_vts;
u32 light_freq, cap_bandfilt, cap_maxband;
u32 cap_gain16_shutter;
u8 average;
int ret;
if (!mode->reg_data)
return -EINVAL;
/* read preview shutter */
ret = ov5640_get_exposure(sensor);
if (ret < 0)
return ret;
prev_shutter = ret;
ret = ov5640_get_binning(sensor);
if (ret < 0)
return ret;
if (ret && mode->id != OV5640_MODE_720P_1280_720 &&
mode->id != OV5640_MODE_1080P_1920_1080)
prev_shutter *= 2;
/* read preview gain */
ret = ov5640_get_gain(sensor);
if (ret < 0)
return ret;
prev_gain16 = ret;
/* get average */
ret = ov5640_read_reg(sensor, OV5640_REG_AVG_READOUT, &average);
if (ret)
return ret;
/* turn off night mode for capture */
ret = ov5640_set_night_mode(sensor);
if (ret < 0)
return ret;
/* Write capture setting */
ret = ov5640_load_regs(sensor, mode);
if (ret < 0)
return ret;
/* read capture VTS */
ret = ov5640_get_vts(sensor);
if (ret < 0)
return ret;
cap_vts = ret;
ret = ov5640_get_hts(sensor);
if (ret < 0)
return ret;
if (ret == 0)
return -EINVAL;
cap_hts = ret;
ret = ov5640_get_sysclk(sensor);
if (ret < 0)
return ret;
if (ret == 0)
return -EINVAL;
cap_sysclk = ret;
/* calculate capture banding filter */
ret = ov5640_get_light_freq(sensor);
if (ret < 0)
return ret;
light_freq = ret;
if (light_freq == 60) {
/* 60Hz */
cap_bandfilt = cap_sysclk * 100 / cap_hts * 100 / 120;
} else {
/* 50Hz */
cap_bandfilt = cap_sysclk * 100 / cap_hts;
}
if (!sensor->prev_sysclk) {
ret = ov5640_get_sysclk(sensor);
if (ret < 0)
return ret;
if (ret == 0)
return -EINVAL;
sensor->prev_sysclk = ret;
}
if (!cap_bandfilt)
return -EINVAL;
cap_maxband = (int)((cap_vts - 4) / cap_bandfilt);
/* calculate capture shutter/gain16 */
if (average > sensor->ae_low && average < sensor->ae_high) {
/* in stable range */
cap_gain16_shutter =
prev_gain16 * prev_shutter *
cap_sysclk / sensor->prev_sysclk *
sensor->prev_hts / cap_hts *
sensor->ae_target / average;
} else {
cap_gain16_shutter =
prev_gain16 * prev_shutter *
cap_sysclk / sensor->prev_sysclk *
sensor->prev_hts / cap_hts;
}
/* gain to shutter */
if (cap_gain16_shutter < (cap_bandfilt * 16)) {
/* shutter < 1/100 */
cap_shutter = cap_gain16_shutter / 16;
if (cap_shutter < 1)
cap_shutter = 1;
cap_gain16 = cap_gain16_shutter / cap_shutter;
if (cap_gain16 < 16)
cap_gain16 = 16;
} else {
if (cap_gain16_shutter > (cap_bandfilt * cap_maxband * 16)) {
/* exposure reach max */
cap_shutter = cap_bandfilt * cap_maxband;
if (!cap_shutter)
return -EINVAL;
cap_gain16 = cap_gain16_shutter / cap_shutter;
} else {
/* 1/100 < (cap_shutter = n/100) =< max */
cap_shutter =
((int)(cap_gain16_shutter / 16 / cap_bandfilt))
* cap_bandfilt;
if (!cap_shutter)
return -EINVAL;
cap_gain16 = cap_gain16_shutter / cap_shutter;
}
}
/* set capture gain */
ret = ov5640_set_gain(sensor, cap_gain16);
if (ret)
return ret;
/* write capture shutter */
if (cap_shutter > (cap_vts - 4)) {
cap_vts = cap_shutter + 4;
ret = ov5640_set_vts(sensor, cap_vts);
if (ret < 0)
return ret;
}
/* set exposure */
return ov5640_set_exposure(sensor, cap_shutter);
}
/*
* if sensor changes inside scaling or subsampling
* change mode directly
*/
static int ov5640_set_mode_direct(struct ov5640_dev *sensor,
const struct ov5640_mode_info *mode)
{
if (!mode->reg_data)
return -EINVAL;
/* Write capture setting */
return ov5640_load_regs(sensor, mode);
}
static int ov5640_set_mode(struct ov5640_dev *sensor)
{
const struct ov5640_mode_info *mode = sensor->current_mode;
const struct ov5640_mode_info *orig_mode = sensor->last_mode;
enum ov5640_downsize_mode dn_mode, orig_dn_mode;
bool auto_gain = sensor->ctrls.auto_gain->val == 1;
bool auto_exp = sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
unsigned long rate;
int ret;
dn_mode = mode->dn_mode;
orig_dn_mode = orig_mode->dn_mode;
/* auto gain and exposure must be turned off when changing modes */
if (auto_gain) {
ret = ov5640_set_autogain(sensor, false);
if (ret)
return ret;
}
if (auto_exp) {
ret = ov5640_set_autoexposure(sensor, false);
if (ret)
goto restore_auto_gain;
}
/*
* All the formats we support have 16 bits per pixel, seems to require
* the same rate than YUV, so we can just use 16 bpp all the time.
*/
rate = mode->vtot * mode->htot * 16;
rate *= ov5640_framerates[sensor->current_fr];
if (sensor->ep.bus_type == V4L2_MBUS_CSI2) {
rate = rate / sensor->ep.bus.mipi_csi2.num_data_lanes;
ret = ov5640_set_mipi_pclk(sensor, rate);
} else {
rate = rate / sensor->ep.bus.parallel.bus_width;
ret = ov5640_set_dvp_pclk(sensor, rate);
}
if (ret < 0)
return 0;
if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
(dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
/*
* change between subsampling and scaling
* go through exposure calculation
*/
ret = ov5640_set_mode_exposure_calc(sensor, mode);
} else {
/*
* change inside subsampling or scaling
* download firmware directly
*/
ret = ov5640_set_mode_direct(sensor, mode);
}
if (ret < 0)
goto restore_auto_exp_gain;
/* restore auto gain and exposure */
if (auto_gain)
ov5640_set_autogain(sensor, true);
if (auto_exp)
ov5640_set_autoexposure(sensor, true);
ret = ov5640_set_binning(sensor, dn_mode != SCALING);
if (ret < 0)
return ret;
ret = ov5640_set_ae_target(sensor, sensor->ae_target);
if (ret < 0)
return ret;
ret = ov5640_get_light_freq(sensor);
if (ret < 0)
return ret;
ret = ov5640_set_bandingfilter(sensor);
if (ret < 0)
return ret;
ret = ov5640_set_virtual_channel(sensor);
if (ret < 0)
return ret;
sensor->pending_mode_change = false;
sensor->last_mode = mode;
return 0;
restore_auto_exp_gain:
if (auto_exp)
ov5640_set_autoexposure(sensor, true);
restore_auto_gain:
if (auto_gain)
ov5640_set_autogain(sensor, true);
return ret;
}
static int ov5640_set_framefmt(struct ov5640_dev *sensor,
struct v4l2_mbus_framefmt *format);
/* restore the last set video mode after chip power-on */
static int ov5640_restore_mode(struct ov5640_dev *sensor)
{
int ret;
/* first load the initial register values */
ret = ov5640_load_regs(sensor, &ov5640_mode_init_data);
if (ret < 0)
return ret;
sensor->last_mode = &ov5640_mode_init_data;
ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x3f,
(ilog2(OV5640_SCLK2X_ROOT_DIV) << 2) |
ilog2(OV5640_SCLK_ROOT_DIV));
if (ret)
return ret;
/* now restore the last capture mode */
ret = ov5640_set_mode(sensor);
if (ret < 0)
return ret;
return ov5640_set_framefmt(sensor, &sensor->fmt);
}
static void ov5640_power(struct ov5640_dev *sensor, bool enable)
{
gpiod_set_value_cansleep(sensor->pwdn_gpio, enable ? 0 : 1);
}
static void ov5640_reset(struct ov5640_dev *sensor)
{
if (!sensor->reset_gpio)
return;
gpiod_set_value_cansleep(sensor->reset_gpio, 0);
/* camera power cycle */
ov5640_power(sensor, false);
usleep_range(5000, 10000);
ov5640_power(sensor, true);
usleep_range(5000, 10000);
gpiod_set_value_cansleep(sensor->reset_gpio, 1);
usleep_range(1000, 2000);
gpiod_set_value_cansleep(sensor->reset_gpio, 0);
usleep_range(20000, 25000);
}
static int ov5640_set_power_on(struct ov5640_dev *sensor)
{
struct i2c_client *client = sensor->i2c_client;
int ret;
ret = clk_prepare_enable(sensor->xclk);
if (ret) {
dev_err(&client->dev, "%s: failed to enable clock\n",
__func__);
return ret;
}
ret = regulator_bulk_enable(OV5640_NUM_SUPPLIES,
sensor->supplies);
if (ret) {
dev_err(&client->dev, "%s: failed to enable regulators\n",
__func__);
goto xclk_off;
}
ov5640_reset(sensor);
ov5640_power(sensor, true);
ret = ov5640_init_slave_id(sensor);
if (ret)
goto power_off;
return 0;
power_off:
ov5640_power(sensor, false);
regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
xclk_off:
clk_disable_unprepare(sensor->xclk);
return ret;
}
static void ov5640_set_power_off(struct ov5640_dev *sensor)
{
ov5640_power(sensor, false);
regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
clk_disable_unprepare(sensor->xclk);
}
static int ov5640_set_power(struct ov5640_dev *sensor, bool on)
{
int ret = 0;
if (on) {
ret = ov5640_set_power_on(sensor);
if (ret)
return ret;
ret = ov5640_restore_mode(sensor);
if (ret)
goto power_off;
/* We're done here for DVP bus, while CSI-2 needs setup. */
if (sensor->ep.bus_type != V4L2_MBUS_CSI2)
return 0;
/*
* Power up MIPI HS Tx and LS Rx; 2 data lanes mode
*
* 0x300e = 0x40
* [7:5] = 010 : 2 data lanes mode (see FIXME note in
* "ov5640_set_stream_mipi()")
* [4] = 0 : Power up MIPI HS Tx
* [3] = 0 : Power up MIPI LS Rx
* [2] = 0 : MIPI interface disabled
*/
ret = ov5640_write_reg(sensor,
OV5640_REG_IO_MIPI_CTRL00, 0x40);
if (ret)
goto power_off;
/*
* Gate clock and set LP11 in 'no packets mode' (idle)
*
* 0x4800 = 0x24
* [5] = 1 : Gate clock when 'no packets'
* [2] = 1 : MIPI bus in LP11 when 'no packets'
*/
ret = ov5640_write_reg(sensor,
OV5640_REG_MIPI_CTRL00, 0x24);
if (ret)
goto power_off;
/*
* Set data lanes and clock in LP11 when 'sleeping'
*
* 0x3019 = 0x70
* [6] = 1 : MIPI data lane 2 in LP11 when 'sleeping'
* [5] = 1 : MIPI data lane 1 in LP11 when 'sleeping'
* [4] = 1 : MIPI clock lane in LP11 when 'sleeping'
*/
ret = ov5640_write_reg(sensor,
OV5640_REG_PAD_OUTPUT00, 0x70);
if (ret)
goto power_off;
/* Give lanes some time to coax into LP11 state. */
usleep_range(500, 1000);
} else {
if (sensor->ep.bus_type == V4L2_MBUS_CSI2) {
/* Reset MIPI bus settings to their default values. */
ov5640_write_reg(sensor,
OV5640_REG_IO_MIPI_CTRL00, 0x58);
ov5640_write_reg(sensor,
OV5640_REG_MIPI_CTRL00, 0x04);
ov5640_write_reg(sensor,
OV5640_REG_PAD_OUTPUT00, 0x00);
}
ov5640_set_power_off(sensor);
}
return 0;
power_off:
ov5640_set_power_off(sensor);
return ret;
}
/* --------------- Subdev Operations --------------- */
static int ov5640_s_power(struct v4l2_subdev *sd, int on)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
int ret = 0;
mutex_lock(&sensor->lock);
/*
* If the power count is modified from 0 to != 0 or from != 0 to 0,
* update the power state.
*/
if (sensor->power_count == !on) {
ret = ov5640_set_power(sensor, !!on);
if (ret)
goto out;
}
/* Update the power count. */
sensor->power_count += on ? 1 : -1;
WARN_ON(sensor->power_count < 0);
out:
mutex_unlock(&sensor->lock);
if (on && !ret && sensor->power_count == 1) {
/* restore controls */
ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
}
return ret;
}
static int ov5640_try_frame_interval(struct ov5640_dev *sensor,
struct v4l2_fract *fi,
u32 width, u32 height)
{
const struct ov5640_mode_info *mode;
enum ov5640_frame_rate rate = OV5640_30_FPS;
int minfps, maxfps, best_fps, fps;
int i;
minfps = ov5640_framerates[OV5640_15_FPS];
maxfps = ov5640_framerates[OV5640_60_FPS];
if (fi->numerator == 0) {
fi->denominator = maxfps;
fi->numerator = 1;
rate = OV5640_60_FPS;
goto find_mode;
}
fps = clamp_val(DIV_ROUND_CLOSEST(fi->denominator, fi->numerator),
minfps, maxfps);
best_fps = minfps;
for (i = 0; i < ARRAY_SIZE(ov5640_framerates); i++) {
int curr_fps = ov5640_framerates[i];
if (abs(curr_fps - fps) < abs(best_fps - fps)) {
best_fps = curr_fps;
rate = i;
}
}
fi->numerator = 1;
fi->denominator = best_fps;
find_mode:
mode = ov5640_find_mode(sensor, rate, width, height, false);
return mode ? rate : -EINVAL;
}
static int ov5640_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
struct v4l2_mbus_framefmt *fmt;
if (format->pad != 0)
return -EINVAL;
mutex_lock(&sensor->lock);
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
fmt = v4l2_subdev_get_try_format(&sensor->sd, cfg,
format->pad);
else
fmt = &sensor->fmt;
format->format = *fmt;
mutex_unlock(&sensor->lock);
return 0;
}
static int ov5640_try_fmt_internal(struct v4l2_subdev *sd,
struct v4l2_mbus_framefmt *fmt,
enum ov5640_frame_rate fr,
const struct ov5640_mode_info **new_mode)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
const struct ov5640_mode_info *mode;
int i;
mode = ov5640_find_mode(sensor, fr, fmt->width, fmt->height, true);
if (!mode)
return -EINVAL;
fmt->width = mode->hact;
fmt->height = mode->vact;
if (new_mode)
*new_mode = mode;
for (i = 0; i < ARRAY_SIZE(ov5640_formats); i++)
if (ov5640_formats[i].code == fmt->code)
break;
if (i >= ARRAY_SIZE(ov5640_formats))
i = 0;
fmt->code = ov5640_formats[i].code;
fmt->colorspace = ov5640_formats[i].colorspace;
fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
return 0;
}
static int ov5640_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
const struct ov5640_mode_info *new_mode;
struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
struct v4l2_mbus_framefmt *fmt;
u64 rate;
int ret;
if (format->pad != 0)
return -EINVAL;
mutex_lock(&sensor->lock);
if (sensor->streaming) {
ret = -EBUSY;
goto out;
}
ret = ov5640_try_fmt_internal(sd, mbus_fmt,
sensor->current_fr, &new_mode);
if (ret)
goto out;
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
else
fmt = &sensor->fmt;
*fmt = *mbus_fmt;
if (new_mode != sensor->current_mode) {
sensor->current_mode = new_mode;
sensor->pending_mode_change = true;
}
if (mbus_fmt->code != sensor->fmt.code)
sensor->pending_fmt_change = true;
rate = sensor->current_mode->vtot * sensor->current_mode->htot;
rate *= ov5640_framerates[sensor->current_fr];
sensor->pixel_rate = rate;
__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,sensor->pixel_rate);
out:
mutex_unlock(&sensor->lock);
return ret;
}
static int ov5640_set_framefmt(struct ov5640_dev *sensor,
struct v4l2_mbus_framefmt *format)
{
int ret = 0;
bool is_rgb = false;
bool is_jpeg = false;
u8 val;
switch (format->code) {
case MEDIA_BUS_FMT_UYVY8_2X8:
/* YUV422, UYVY */
val = 0x3f;
break;
case MEDIA_BUS_FMT_YUYV8_2X8:
/* YUV422, YUYV */
val = 0x30;
break;
case MEDIA_BUS_FMT_RGB565_2X8_LE:
/* RGB565 {g[2:0],b[4:0]},{r[4:0],g[5:3]} */
val = 0x6F;
is_rgb = true;
break;
case MEDIA_BUS_FMT_RGB565_2X8_BE:
/* RGB565 {r[4:0],g[5:3]},{g[2:0],b[4:0]} */
val = 0x61;
is_rgb = true;
break;
case MEDIA_BUS_FMT_JPEG_1X8:
/* YUV422, YUYV */
val = 0x30;
is_jpeg = true;
break;
default:
return -EINVAL;
}
/* FORMAT CONTROL00: YUV and RGB formatting */
ret = ov5640_write_reg(sensor, OV5640_REG_FORMAT_CONTROL00, val);
if (ret)
return ret;
/* FORMAT MUX CONTROL: ISP YUV or RGB */
ret = ov5640_write_reg(sensor, OV5640_REG_ISP_FORMAT_MUX_CTRL,
is_rgb ? 0x01 : 0x00);
if (ret)
return ret;
/*
* TIMING TC REG21:
* - [5]: JPEG enable
*/
ret = ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
BIT(5), is_jpeg ? BIT(5) : 0);
if (ret)
return ret;
/*
* SYSTEM RESET02:
* - [4]: Reset JFIFO
* - [3]: Reset SFIFO
* - [2]: Reset JPEG
*/
ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_RESET02,
BIT(4) | BIT(3) | BIT(2),
is_jpeg ? 0 : (BIT(4) | BIT(3) | BIT(2)));
if (ret)
return ret;
/*
* CLOCK ENABLE02:
* - [5]: Enable JPEG 2x clock
* - [3]: Enable JPEG clock
*/
return ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE02,
BIT(5) | BIT(3),
is_jpeg ? (BIT(5) | BIT(3)) : 0);
}
/*
* Sensor Controls.
*/
static int ov5640_set_ctrl_hue(struct ov5640_dev *sensor, int value)
{
int ret;
if (value) {
ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
BIT(0), BIT(0));
if (ret)
return ret;
ret = ov5640_write_reg16(sensor, OV5640_REG_SDE_CTRL1, value);
} else {
ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(0), 0);
}
return ret;
}
static int ov5640_set_ctrl_contrast(struct ov5640_dev *sensor, int value)
{
int ret;
if (value) {
ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
BIT(2), BIT(2));
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL5,
value & 0xff);
} else {
ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(2), 0);
}
return ret;
}
static int ov5640_set_ctrl_saturation(struct ov5640_dev *sensor, int value)
{
int ret;
if (value) {
ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
BIT(1), BIT(1));
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL3,
value & 0xff);
if (ret)
return ret;
ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL4,
value & 0xff);
} else {
ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(1), 0);
}
return ret;
}
static int ov5640_set_ctrl_white_balance(struct ov5640_dev *sensor, int awb)
{
int ret;
ret = ov5640_mod_reg(sensor, OV5640_REG_AWB_MANUAL_CTRL,
BIT(0), awb ? 0 : 1);
if (ret)
return ret;
if (!awb) {
u16 red = (u16)sensor->ctrls.red_balance->val;
u16 blue = (u16)sensor->ctrls.blue_balance->val;
ret = ov5640_write_reg16(sensor, OV5640_REG_AWB_R_GAIN, red);
if (ret)
return ret;
ret = ov5640_write_reg16(sensor, OV5640_REG_AWB_B_GAIN, blue);
}
return ret;
}
static int ov5640_set_ctrl_exposure(struct ov5640_dev *sensor,
enum v4l2_exposure_auto_type auto_exposure)
{
struct ov5640_ctrls *ctrls = &sensor->ctrls;
bool auto_exp = (auto_exposure == V4L2_EXPOSURE_AUTO);
int ret = 0;
if (ctrls->auto_exp->is_new) {
ret = ov5640_set_autoexposure(sensor, auto_exp);
if (ret)
return ret;
}
if (!auto_exp && ctrls->exposure->is_new) {
u16 max_exp;
ret = ov5640_read_reg16(sensor, OV5640_REG_AEC_PK_VTS,
&max_exp);
if (ret)
return ret;
ret = ov5640_get_vts(sensor);
if (ret < 0)
return ret;
max_exp += ret;
ret = 0;
if (ctrls->exposure->val < max_exp)
ret = ov5640_set_exposure(sensor, ctrls->exposure->val);
}
return ret;
}
static int ov5640_set_ctrl_gain(struct ov5640_dev *sensor, bool auto_gain)
{
struct ov5640_ctrls *ctrls = &sensor->ctrls;
int ret = 0;
if (ctrls->auto_gain->is_new) {
ret = ov5640_set_autogain(sensor, auto_gain);
if (ret)
return ret;
}
if (!auto_gain && ctrls->gain->is_new)
ret = ov5640_set_gain(sensor, ctrls->gain->val);
return ret;
}
static int ov5640_set_ctrl_test_pattern(struct ov5640_dev *sensor, int value)
{
return ov5640_mod_reg(sensor, OV5640_REG_PRE_ISP_TEST_SET1,
0xa4, value ? 0xa4 : 0);
}
static int ov5640_set_ctrl_light_freq(struct ov5640_dev *sensor, int value)
{
int ret;
ret = ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL01, BIT(7),
(value == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) ?
0 : BIT(7));
if (ret)
return ret;
return ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL00, BIT(2),
(value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
BIT(2) : 0);
}
static int ov5640_set_ctrl_hflip(struct ov5640_dev *sensor, int value)
{
/*
* If sensor is mounted upside down, mirror logic is inversed.
*
* Sensor is a BSI (Back Side Illuminated) one,
* so image captured is physically mirrored.
* This is why mirror logic is inversed in
* order to cancel this mirror effect.
*/
/*
* TIMING TC REG21:
* - [2]: ISP mirror
* - [1]: Sensor mirror
*/
return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
BIT(2) | BIT(1),
(!(value ^ sensor->upside_down)) ?
(BIT(2) | BIT(1)) : 0);
}
static int ov5640_set_ctrl_vflip(struct ov5640_dev *sensor, int value)
{
/* If sensor is mounted upside down, flip logic is inversed */
/*
* TIMING TC REG20:
* - [2]: ISP vflip
* - [1]: Sensor vflip
*/
return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG20,
BIT(2) | BIT(1),
(value ^ sensor->upside_down) ?
(BIT(2) | BIT(1)) : 0);
}
static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
struct ov5640_dev *sensor = to_ov5640_dev(sd);
int val;
/* v4l2_ctrl_lock() locks our own mutex */
switch (ctrl->id) {
case V4L2_CID_AUTOGAIN:
val = ov5640_get_gain(sensor);
if (val < 0)
return val;
sensor->ctrls.gain->val = val;
break;
case V4L2_CID_EXPOSURE_AUTO:
val = ov5640_get_exposure(sensor);
if (val < 0)
return val;
sensor->ctrls.exposure->val = val;
break;
}
return 0;
}
static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
struct ov5640_dev *sensor = to_ov5640_dev(sd);
int ret;
/* v4l2_ctrl_lock() locks our own mutex */
/*
* If the device is not powered up by the host driver do
* not apply any controls to H/W at this time. Instead
* the controls will be restored right after power-up.
*/
if (sensor->power_count == 0)
return 0;
switch (ctrl->id) {
case V4L2_CID_AUTOGAIN:
ret = ov5640_set_ctrl_gain(sensor, ctrl->val);
break;
case V4L2_CID_EXPOSURE_AUTO:
ret = ov5640_set_ctrl_exposure(sensor, ctrl->val);
break;
case V4L2_CID_AUTO_WHITE_BALANCE:
ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val);
break;
case V4L2_CID_HUE:
ret = ov5640_set_ctrl_hue(sensor, ctrl->val);
break;
case V4L2_CID_CONTRAST:
ret = ov5640_set_ctrl_contrast(sensor, ctrl->val);
break;
case V4L2_CID_SATURATION:
ret = ov5640_set_ctrl_saturation(sensor, ctrl->val);
break;
case V4L2_CID_TEST_PATTERN:
ret = ov5640_set_ctrl_test_pattern(sensor, ctrl->val);
break;
case V4L2_CID_POWER_LINE_FREQUENCY:
ret = ov5640_set_ctrl_light_freq(sensor, ctrl->val);
break;
case V4L2_CID_HFLIP:
ret = ov5640_set_ctrl_hflip(sensor, ctrl->val);
break;
case V4L2_CID_VFLIP:
ret = ov5640_set_ctrl_vflip(sensor, ctrl->val);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct v4l2_ctrl_ops ov5640_ctrl_ops = {
.g_volatile_ctrl = ov5640_g_volatile_ctrl,
.s_ctrl = ov5640_s_ctrl,
};
static const char * const test_pattern_menu[] = {
"Disabled",
"Color bars",
};
static int ov5640_init_controls(struct ov5640_dev *sensor)
{
const struct v4l2_ctrl_ops *ops = &ov5640_ctrl_ops;
struct ov5640_ctrls *ctrls = &sensor->ctrls;
struct v4l2_ctrl_handler *hdl = &ctrls->handler;
int ret;
v4l2_ctrl_handler_init(hdl, 32);
/* we can use our own mutex for the ctrl lock */
hdl->lock = &sensor->lock;
/* Clock related controls */
ctrls->pixel_rate =
v4l2_ctrl_new_std(hdl, ops,
V4L2_CID_PIXEL_RATE, 0, INT_MAX, 1,
55969920);
ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
/* Auto/manual white balance */
ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
V4L2_CID_AUTO_WHITE_BALANCE,
0, 1, 1, 1);
ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
0, 4095, 1, 0);
ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
0, 4095, 1, 0);
/* Auto/manual exposure */
ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
V4L2_CID_EXPOSURE_AUTO,
V4L2_EXPOSURE_MANUAL, 0,
V4L2_EXPOSURE_AUTO);
ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
0, 65535, 1, 0);
/* Auto/manual gain */
ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
0, 1, 1, 1);
ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
0, 1023, 1, 0);
ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
0, 255, 1, 64);
ctrls->hue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE,
0, 359, 1, 0);
ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
0, 255, 1, 0);
ctrls->test_pattern =
v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
ARRAY_SIZE(test_pattern_menu) - 1,
0, 0, test_pattern_menu);
ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP,
0, 1, 1, 0);
ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP,
0, 1, 1, 0);
ctrls->light_freq =
v4l2_ctrl_new_std_menu(hdl, ops,
V4L2_CID_POWER_LINE_FREQUENCY,
V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
if (hdl->error) {
ret = hdl->error;
goto free_ctrls;
}
ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
sensor->sd.ctrl_handler = hdl;
return 0;
free_ctrls:
v4l2_ctrl_handler_free(hdl);
return ret;
}
static int ov5640_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_size_enum *fse)
{
if (fse->pad != 0)
return -EINVAL;
if (fse->index >= OV5640_NUM_MODES)
return -EINVAL;
fse->min_width =
ov5640_mode_data[fse->index].hact;
fse->max_width = fse->min_width;
fse->min_height =
ov5640_mode_data[fse->index].vact;
fse->max_height = fse->min_height;
return 0;
}
static int ov5640_enum_frame_interval(
struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_frame_interval_enum *fie)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
struct v4l2_fract tpf;
int ret;
if (fie->pad != 0)
return -EINVAL;
if (fie->index >= OV5640_NUM_FRAMERATES)
return -EINVAL;
tpf.numerator = 1;
tpf.denominator = ov5640_framerates[fie->index];
ret = ov5640_try_frame_interval(sensor, &tpf,
fie->width, fie->height);
if (ret < 0)
return -EINVAL;
fie->interval = tpf;
return 0;
}
static int ov5640_g_frame_interval(struct v4l2_subdev *sd,
struct v4l2_subdev_frame_interval *fi)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
mutex_lock(&sensor->lock);
fi->interval = sensor->frame_interval;
mutex_unlock(&sensor->lock);
return 0;
}
static int ov5640_s_frame_interval(struct v4l2_subdev *sd,
struct v4l2_subdev_frame_interval *fi)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
const struct ov5640_mode_info *mode;
int frame_rate, ret = 0;
u64 rate;
if (fi->pad != 0)
return -EINVAL;
mutex_lock(&sensor->lock);
if (sensor->streaming) {
ret = -EBUSY;
goto out;
}
mode = sensor->current_mode;
frame_rate = ov5640_try_frame_interval(sensor, &fi->interval,
mode->hact, mode->vact);
if (frame_rate < 0) {
/* Always return a valid frame interval value */
fi->interval = sensor->frame_interval;
goto out;
}
mode = ov5640_find_mode(sensor, frame_rate, mode->hact,
mode->vact, true);
if (!mode) {
ret = -EINVAL;
goto out;
}
if (mode != sensor->current_mode ||
frame_rate != sensor->current_fr) {
sensor->current_fr = frame_rate;
sensor->frame_interval = fi->interval;
sensor->current_mode = mode;
sensor->pending_mode_change = true;
rate = sensor->current_mode->vtot * sensor->current_mode->htot;
rate *= ov5640_framerates[sensor->current_fr];
sensor->pixel_rate = rate;
__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
sensor->pixel_rate);
}
out:
mutex_unlock(&sensor->lock);
return ret;
}
static int ov5640_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_mbus_code_enum *code)
{
if (code->pad != 0)
return -EINVAL;
if (code->index >= ARRAY_SIZE(ov5640_formats))
return -EINVAL;
code->code = ov5640_formats[code->index].code;
return 0;
}
static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
{
struct ov5640_dev *sensor = to_ov5640_dev(sd);
int ret = 0;
mutex_lock(&sensor->lock);
if (sensor->streaming == !enable) {
if (enable && sensor->pending_mode_change) {
ret = ov5640_set_mode(sensor);
if (ret)
goto out;
}
if (enable && sensor->pending_fmt_change) {
ret = ov5640_set_framefmt(sensor, &sensor->fmt);
if (ret)
goto out;
sensor->pending_fmt_change = false;
}
if (sensor->ep.bus_type == V4L2_MBUS_CSI2)
ret = ov5640_set_stream_mipi(sensor, enable);
else
ret = ov5640_set_stream_dvp(sensor, enable);
if (!ret)
sensor->streaming = enable;
}
out:
mutex_unlock(&sensor->lock);
return ret;
}
static const struct v4l2_subdev_core_ops ov5640_core_ops = {
.s_power = ov5640_s_power,
.log_status = v4l2_ctrl_subdev_log_status,
.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
.unsubscribe_event = v4l2_event_subdev_unsubscribe,
};
static const struct v4l2_subdev_video_ops ov5640_video_ops = {
.g_frame_interval = ov5640_g_frame_interval,
.s_frame_interval = ov5640_s_frame_interval,
.s_stream = ov5640_s_stream,
};
static const struct v4l2_subdev_pad_ops ov5640_pad_ops = {
.enum_mbus_code = ov5640_enum_mbus_code,
.get_fmt = ov5640_get_fmt,
.set_fmt = ov5640_set_fmt,
.enum_frame_size = ov5640_enum_frame_size,
.enum_frame_interval = ov5640_enum_frame_interval,
};
static const struct v4l2_subdev_ops ov5640_subdev_ops = {
.core = &ov5640_core_ops,
.video = &ov5640_video_ops,
.pad = &ov5640_pad_ops,
};
static int ov5640_get_regulators(struct ov5640_dev *sensor)
{
int i;
for (i = 0; i < OV5640_NUM_SUPPLIES; i++)
sensor->supplies[i].supply = ov5640_supply_name[i];
return devm_regulator_bulk_get(&sensor->i2c_client->dev,
OV5640_NUM_SUPPLIES,
sensor->supplies);
}
static int ov5640_check_chip_id(struct ov5640_dev *sensor)
{
struct i2c_client *client = sensor->i2c_client;
int ret = 0;
u16 chip_id;
ov5640_init_slave_id(sensor);
/*ret = ov5640_set_power_on(sensor); //cispl
if (ret)
return ret;*/
ret = ov5640_cispl_read_reg(sensor, OV5640_REG_SYS_CARAVEL, &chip_id);
//ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
if (ret) {
dev_err(&client->dev, "%s: failed to read chip identifier\n",
__func__);
// goto power_off;
}
if (chip_id != 0x5640) {
dev_err(&client->dev, "%s: wrong chip identifier, expected 0x5640, got 0x%x\n",
__func__, chip_id);
ret = -ENXIO;
}
//power_off:
// ov5640_set_power_off(sensor);
// return ret;
}
static int ov5640_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct device *dev = &client->dev;
struct fwnode_handle *endpoint;
struct ov5640_dev *sensor;
struct v4l2_mbus_framefmt *fmt;
u32 rotation;
int ret;
sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
if (!sensor)
return -ENOMEM;
sensor->i2c_client = client;
/*
* default init sequence initialize sensor to
* YUV422 UYVY VGA@30fps
*/
fmt = &sensor->fmt;
fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
fmt->colorspace = V4L2_COLORSPACE_JPEG;
fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
fmt->width = 1920;
fmt->height = 1080;
fmt->field = V4L2_FIELD_NONE;
sensor->frame_interval.numerator = 1;
sensor->frame_interval.denominator = ov5640_framerates[OV5640_30_FPS];
sensor->current_fr = OV5640_30_FPS;
sensor->current_mode =
&ov5640_mode_data[OV5640_MODE_1080P_1920_1080];
sensor->last_mode = sensor->current_mode;
sensor->ae_target = 52;
/* optional indication of physical rotation of sensor */
ret = fwnode_property_read_u32(dev_fwnode(&client->dev), "rotation",
&rotation);
if (!ret) {
switch (rotation) {
case 180:
sensor->upside_down = true;
/* fall through */
case 0:
break;
default:
dev_warn(dev, "%u degrees rotation is not supported, ignoring...\n",
rotation);
}
}
endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev),
NULL);
if (!endpoint) {
dev_err(dev, "endpoint node not found\n");
return -EINVAL;
}
ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
fwnode_handle_put(endpoint);
if (ret) {
dev_err(dev, "Could not parse endpoint\n");
return ret;
}
/* get system clock (xclk) */
/*sensor->xclk = devm_clk_get(dev, "xclk");
if (IS_ERR(sensor->xclk)) {
dev_err(dev, "failed to get xclk\n");
return PTR_ERR(sensor->xclk);
}
sensor->xclk_freq = clk_get_rate(sensor->xclk);
if (sensor->xclk_freq < OV5640_XCLK_MIN ||
sensor->xclk_freq > OV5640_XCLK_MAX) {
dev_err(dev, "xclk frequency out of range: %d Hz\n",
sensor->xclk_freq);
return -EINVAL;
}*/
sensor->xclk_freq = OV5640_XCLK_MAX;
/* request optional power down pin */
sensor->pwdn_gpio = devm_gpiod_get_optional(dev, "powerdown",
GPIOD_OUT_HIGH);
/* request optional reset pin */
sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
v4l2_i2c_subdev_init(&sensor->sd, client, &ov5640_subdev_ops);
sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
V4L2_SUBDEV_FL_HAS_EVENTS;
sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
if (ret)
return ret;
ret = ov5640_get_regulators(sensor);
if (ret)
return ret;
mutex_init(&sensor->lock);
ret = ov5640_check_chip_id(sensor);
// if (ret)
// goto entity_cleanup;
// ret = ov5640_init_controls(sensor);
// if (ret)
// goto entity_cleanup;
ret = v4l2_async_register_subdev(&sensor->sd);
if (ret)
goto free_ctrls;
return 0;
free_ctrls:
v4l2_ctrl_handler_free(&sensor->ctrls.handler);
entity_cleanup:
mutex_destroy(&sensor->lock);
media_entity_cleanup(&sensor->sd.entity);
return ret;
}
static int ov5640_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct ov5640_dev *sensor = to_ov5640_dev(sd);
v4l2_async_unregister_subdev(&sensor->sd);
mutex_destroy(&sensor->lock);
media_entity_cleanup(&sensor->sd.entity);
v4l2_ctrl_handler_free(&sensor->ctrls.handler);
return 0;
}
static const struct i2c_device_id ov5640_id[] = {
{"ov5640", 0},
{},
};
MODULE_DEVICE_TABLE(i2c, ov5640_id);
static const struct of_device_id ov5640_dt_ids[] = {
{ .compatible = "ovti,ov5640" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ov5640_dt_ids);
static struct i2c_driver ov5640_i2c_driver = {
.driver = {
.name = "ov5640",
.of_match_table = ov5640_dt_ids,
},
.id_table = ov5640_id,
.probe = ov5640_probe,
.remove = ov5640_remove,
};
module_i2c_driver(ov5640_i2c_driver);
MODULE_DESCRIPTION("OV5640 MIPI Camera Subdev Driver");
MODULE_LICENSE("GPL");
Output of :
U-Boot 2019.01 (Dec 23 2021 - 18:29:37 +0530)
CPU : DRA752-GP ES2.0
Model: TI AM5728 BeagleBoard-X15 rev C
Board: BeagleBoard X15 REV C.00
DRAM: 2 GiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Loading Environment from FAT... OK
Net:
Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
1490 bytes read in 1 ms (1.4 MiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
1 bytes read in 1 ms (1000 Bytes/s)
Already setup.
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
4403712 bytes read in 196 ms (21.4 MiB/s)
131858 bytes read in 8 ms (15.7 MiB/s)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8ffdc000, end 8ffff311 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.19.59-g5f8c1c6121 (root@ubuntu-OptiPlex-3040) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #11 SMP PREEMPT Fri Dec 31 14:58:49 IST 2021
[ 0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[ 0.000000] CPU: div instructions available: patching division code
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[ 0.000000] OF: fdt: Machine model: TI AM5728 BeagleBoard-X15 rev C
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[ 0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[ 0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[ 0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[ 0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[ 0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
[ 0.000000] OMAP4: Map 0x00000000ffd00000 to (ptrval) for dram barrier
[ 0.000000] DRA752 ES2.0
[ 0.000000] random: get_random_bytes called from start_kernel+0xb4/0x470 with crng_init=0
[ 0.000000] percpu: Embedded 16 pages/cpu s36492 r8192 d20852 u65536
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 472640
[ 0.000000] Kernel command line: console=ttyS2,115200n8 root=PARTUUID=0f3f03ba-02 rw rootfstype=ext4 rootwait
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Memory: 1673648K/1897472K available (10240K kernel code, 333K rwdata, 2772K rodata, 2048K init, 269K bss, 35408K reserved, 188416K cma-reserved, 1283072K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (12256 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (2048 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 334 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) ( 270 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] OMAP clockevent source: timer1 at 32786 Hz
[ 0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[ 0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[ 0.000018] Switching to timer-based delay loop, resolution 162ns
[ 0.000300] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[ 0.000309] OMAP clocksource: 32k_counter at 32768 Hz
[ 0.000817] Console: colour dummy device 80x30
[ 0.000860] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[ 0.000877] pid_max: default: 32768 minimum: 301
[ 0.000998] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.001014] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.001567] CPU: Testing write buffer coherency: ok
[ 0.001606] CPU0: Spectre v2: using ICIALLU workaround
[ 0.001816] /cpus/cpu@0 missing clock-frequency property
[ 0.001836] /cpus/cpu@1 missing clock-frequency property
[ 0.001849] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.059905] Setting up static identity map for 0x80200000 - 0x80200060
[ 0.079916] rcu: Hierarchical SRCU implementation.
[ 0.100105] EFI services will not be available.
[ 0.119979] smp: Bringing up secondary CPUs ...
[ 0.200375] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.200380] CPU1: Spectre v2: using ICIALLU workaround
[ 0.200503] smp: Brought up 1 node, 2 CPUs
[ 0.200515] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[ 0.200524] CPU: All CPU(s) started in HYP mode.
[ 0.200532] CPU: Virtualization extensions available.
[ 0.201085] devtmpfs: initialized
[ 0.220091] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[ 0.220377] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.220422] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.223526] pinctrl core: initialized pinctrl subsystem
[ 0.224026] DMI not present or invalid.
[ 0.224299] NET: Registered protocol family 16
[ 0.225436] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.226376] omap_hwmod: l3_main_2 using broken dt data from ocp
[ 0.328731] wkupaon_cm:clk:0068:0: failed to disable
[ 0.428463] cpuidle: using governor ladder
[ 0.428498] cpuidle: using governor menu
[ 0.438700] OMAP GPIO hardware version 0.1
[ 0.462841] No ATAGs?
[ 0.462918] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[ 0.462932] hw-breakpoint: maximum watchpoint size is 8 bytes.
[ 0.463461] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[ 0.463474] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[ 0.464104] OMAP DMA hardware revision 0.0
[ 0.475134] edma 43300000.edma: memcpy is disabled
[ 0.478391] edma 43300000.edma: TI EDMA DMA engine driver
[ 0.485284] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[ 0.486072] evm_5v0: supplied by main_12v0
[ 0.489402] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[ 0.489581] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[ 0.489816] omap-iommu 58882000.mmu: 58882000.mmu registered
[ 0.490067] omap-iommu 55082000.mmu: 55082000.mmu registered
[ 0.490429] omap-iommu 41501000.mmu: 41501000.mmu registered
[ 0.490602] omap-iommu 41502000.mmu: 41502000.mmu registered
[ 0.490875] iommu: Adding device 58820000.ipu to group 1
[ 0.490954] iommu: Adding device 55020000.ipu to group 2
[ 0.491078] iommu: Adding device 40800000.dsp to group 0
[ 0.491304] iommu: Adding device 41000000.dsp to group 3
[ 0.492530] SCSI subsystem initialized
[ 0.493571] palmas 0-0058: Irq flag is 0x00000008
[ 0.521299] palmas 0-0058: Muxing GPIO 2f, PWM 0, LED 0
[ 0.522891] SMPS12: supplied by regulator-dummy
[ 0.524568] SMPS3: supplied by regulator-dummy
[ 0.526218] SMPS45: supplied by regulator-dummy
[ 0.528014] SMPS6: supplied by regulator-dummy
[ 0.529450] SMPS7: supplied by regulator-dummy
[ 0.530822] SMPS8: supplied by regulator-dummy
[ 0.532078] SMPS9: supplied by regulator-dummy
[ 0.532749] LDO1: supplied by regulator-dummy
[ 0.539812] LDO2: supplied by regulator-dummy
[ 0.540309] random: fast init done
[ 0.549682] LDO3: supplied by regulator-dummy
[ 0.559688] LDO4: supplied by regulator-dummy
[ 0.569715] LDO5: supplied by regulator-dummy
[ 0.570388] LDO6: supplied by regulator-dummy
[ 0.571077] LDO7: supplied by regulator-dummy
[ 0.571760] LDO8: supplied by regulator-dummy
[ 0.572457] LDO9: supplied by regulator-dummy
[ 0.579736] LDOLN: supplied by regulator-dummy
[ 0.589760] LDOUSB: supplied by regulator-dummy
[ 0.602133] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[ 0.602717] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[ 0.602928] media: Linux media interface: v0.10
[ 0.602968] videodev: Linux video capture interface: v2.00
[ 0.603040] pps_core: LinuxPPS API ver. 1 registered
[ 0.603050] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.603071] PTP clock support registered
[ 0.603106] EDAC MC: Ver: 3.0.0
[ 0.603892] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[ 0.604137] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[ 0.604620] Advanced Linux Sound Architecture Driver Initialized.
[ 0.605390] clocksource: Switched to clocksource arch_sys_counter
[ 0.613605] NET: Registered protocol family 2
[ 0.614191] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[ 0.614221] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.614284] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.614410] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.614481] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.614516] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.614644] NET: Registered protocol family 1
[ 0.615052] RPC: Registered named UNIX socket transport module.
[ 0.615063] RPC: Registered udp transport module.
[ 0.615072] RPC: Registered tcp transport module.
[ 0.615080] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.616116] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[ 0.616303] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[ 0.617276] Initialise system trusted keyrings
[ 0.617415] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[ 0.622237] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.622702] NFS: Registering the id_resolver key type
[ 0.622725] Key type id_resolver registered
[ 0.622735] Key type id_legacy registered
[ 0.622777] ntfs: driver 2.1.32 [Flags: R/O].
[ 0.624328] Key type asymmetric registered
[ 0.624340] Asymmetric key parser 'x509' registered
[ 0.624390] bounce: pool size: 64 pages
[ 0.624424] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[ 0.624435] io scheduler noop registered
[ 0.624444] io scheduler deadline registered
[ 0.624538] io scheduler cfq registered (default)
[ 0.624550] io scheduler mq-deadline registered
[ 0.624559] io scheduler kyber registered
[ 0.630264] pinctrl-single 4a003400.pinmux: 282 pins, size 1128
[ 0.633797] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[ 0.634057] dra7-pcie 51000000.pcie: WA for Errata i870 not applied
[ 0.634146] dra7-pcie 51000000.pcie: host bridge /ocp/axi@0/pcie@51000000 ranges:
[ 0.634187] dra7-pcie 51000000.pcie: IO 0x20003000..0x20012fff -> 0x00000000
[ 0.634216] dra7-pcie 51000000.pcie: MEM 0x20013000..0x2fffffff -> 0x20013000
[ 1.634502] dra7-pcie 51000000.pcie: Phy link never came up
[ 1.634640] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[ 1.634655] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 1.634667] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 1.634679] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[ 1.641083] PCI: bus0: Fast back to back transfers disabled
[ 1.646946] PCI: bus1: Fast back to back transfers enabled
[ 1.646990] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[ 1.647010] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 1.647327] pcieport 0000:00:00.0: Signaling PME with IRQ 172
[ 1.647457] pcieport 0000:00:00.0: AER enabled with IRQ 172
[ 1.651119] vdd_3v3: supplied by regen1
[ 1.651348] aic_dvdd_fixed: supplied by vdd_3v3
[ 1.651412] vtt_fixed: supplied by smps3
[ 1.695299] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
[ 1.698822] console [ttyS2] disabled
[ 1.698878] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[ 2.804396] console [ttyS2] enabled
[ 2.810237] omap_rng 48090000.rng: Random Number Generator ver. 20
[ 2.810589] random: crng init done
[ 2.817362] omapdss_dss 58000000.dss: Linked as a consumer to regulator.22
[ 2.826959] DSS: OMAP DSS rev 6.1
[ 2.833170] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.16
[ 2.840732] omapdss_hdmi5 58040000.encoder: Dropping the link to regulator.16
[ 2.861020] brd: module loaded
[ 2.870184] loop: module loaded
[ 2.877300] libphy: Fixed MDIO Bus: probed
[ 2.935417] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[ 2.943113] libphy: 48485000.mdio: probed
[ 2.951851] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver Micrel KSZ9031 Gigabit PHY
[ 2.961574] davinci_mdio 48485000.mdio: phy[2]: device 48485000.mdio:02, driver Micrel KSZ9031 Gigabit PHY
[ 2.971825] cpsw 48484000.ethernet: Detected MACID = d4:36:39:26:8c:68
[ 2.978443] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[ 2.984827] cpsw 48484000.ethernet: ALE Table size 1024
[ 2.990134] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[ 2.998113] cpsw 48484000.ethernet: cpsw: Detected MACID = d4:36:39:26:8c:69
[ 3.006393] i2c /dev entries driver
[ 3.013031] gpio-fan gpio_fan: GPIO fan initialized
[ 3.019094] tmp102 0-0048: initialized
[ 3.025888] cpu cpu0: Linked as a consumer to regulator.6
[ 3.031383] cpu cpu0: Linked as a consumer to regulator.29
[ 3.038524] sdhci: Secure Digital Host Controller Interface driver
[ 3.044734] sdhci: Copyright(c) Pierre Ossman
[ 3.050359] sdhci-pltfm: SDHCI platform and OF driver helper
[ 3.056697] omap_gpio 4805d000.gpio: Could not set line 27 debounce to 200000 microseconds (-22)
[ 3.065557] sdhci-omap 4809c000.mmc: Got CD GPIO
[ 3.070352] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.28
[ 3.077389] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.13
[ 3.084257] sdhci-omap 4809c000.mmc: Dropping the link to regulator.13
[ 3.090899] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.3
[ 3.097825] sdhci-omap 4809c000.mmc: Linked as a consumer to regulator.13
[ 3.104763] sdhci-omap 4809c000.mmc: no pinctrl state for ddr_3_3v mode
[ 3.135908] mmc0: SDHCI controller on 4809c000.mmc [4809c000.mmc] using ADMA
[ 3.144042] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.3
[ 3.150879] sdhci-omap 480b4000.mmc: Dropping the link to regulator.3
[ 3.157664] sdhci-omap 480b4000.mmc: Linked as a consumer to regulator.3
[ 3.188176] mmc1: SDHCI controller on 480b4000.mmc [480b4000.mmc] using ADMA
[ 3.196671] ledtrig-cpu: registered to indicate activity on CPUs
[ 3.209023] NET: Registered protocol family 10
[ 3.214246] Segment Routing with IPv6
[ 3.218024] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.224368] NET: Registered protocol family 17
[ 3.229057] Key type dns_resolver registered
[ 3.233474] Registering SWP/SWPB emulation handler
[ 3.238338] omap_voltage_late_init: Voltage driver support not added
[ 3.244739] Power Management for TI OMAP4+ devices.
[ 3.250243] Loading compiled-in X.509 certificates
[ 3.260069] mmc0: host does not support reading read-only switch, assuming write-enable
[ 3.271059] mmc0: new high speed SDHC card at address aaaa
[ 3.277806] mmc1: new DDR MMC card at address 0001
[ 3.282883] dmm 4e000000.dmm: workaround for errata i878 in use
[ 3.287314] mmcblk0: mmc0:aaaa SD32G 29.7 GiB
[ 3.293764] mmcblk1: mmc1:0001 M62704 3.53 GiB
[ 3.298373] dmm 4e000000.dmm: initialized all PAT entries
[ 3.298748] mmcblk1boot0: mmc1:0001 M62704 partition 1 2.00 MiB
[ 3.310136] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.16
[ 3.310650] mmcblk1boot1: mmc1:0001 M62704 partition 2 2.00 MiB
[ 3.317667] omapdss_hdmi5 58040000.encoder: Dropping the link to regulator.16
[ 3.330915] mmcblk1rpmb: mmc1:0001 M62704 partition 3 512 KiB, chardev (244:0)
[ 3.338254] mmcblk0: p1 p2
[ 3.341853] omapdss_hdmi5 58040000.encoder: Linked as a consumer to regulator.16
[ 3.342447] mmcblk1: p1
[ 3.353345] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[ 3.361350] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
[ 3.370063] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 3.376725] [drm] No driver support for vblank timestamp query.
[ 3.382685] [drm] Cannot find any crtc or sizes
[ 3.387923] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[ 3.395522] hctosys: unable to open rtc device (rtc0)
[ 3.401184] aic_dvdd_fixed: disabling
[ 3.405023] ldousb: disabling
[ 3.408306] ALSA device list:
[ 3.411285] No soundcards found.
[ 3.434404] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[ 3.442580] VFS: Mounted root (ext4 filesystem) on device 179:2.
[ 3.456524] devtmpfs: mounted
[ 3.460379] Freeing unused kernel memory: 2048K
[ 3.465026] Run /sbin/init as init process
[ 3.823309] systemd[1]: System time before build time, advancing clock.
[ 3.857551] systemd[1]: systemd 239 running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
[ 3.879437] systemd[1]: Detected architecture arm.
Welcome to Arago 2019.07!
[ 3.916489] systemd[1]: Set hostname to <am57xx-evm>.
[ 4.095030] systemd[1]: File /lib/systemd/system/systemd-journald.service:36 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling.
[ 4.112214] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
[ 4.322359] systemd[1]: Listening on initctl Compatibility Named Pipe.
[ OK ] Listening on initctl Compatibility Named Pipe.
[ 4.355755] systemd[1]: Reached target Remote File Systems.
[ OK ] Reached target Remote File Systems.
[ 4.385842] systemd[1]: Listening on udev Control Socket.
[ OK ] Listening on udev Control Socket.
[ 4.415450] [drm] Cannot find any crtc or sizes
[ 4.415537] systemd[1]: Reached target Swap.
[ OK ] Reached target Swap.
[ 4.445685] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[ OK ] Started Dispatch Password Requests to Console Directory Watch.
[ OK ] Listening on Journal Socket.
[ OK ] Started Hardware RNG Entropy Gatherer Daemon.
Starting Load Kernel Modules...
Mounting Kernel Debug File System...
[ 4.618329] cmemk: loading out-of-tree module taints kernel.
[ 4.625117] CMEMK module: reference Linux version 4.19.59
Mounting POSIX Message Queue File System...
[ 4.631211] allocated heap buffer 0x40500000 of size 0x100000
[ 4.640423] cmemk initialized
[ 4.650865] cryptodev: driver 1.9 loaded.
Starting Create list of required st…ce nodes for the current kernel...
Starting Remount Root and Kernel File Systems...
[ 4.704568] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
[ 4.717326] usbcore: registered new interface driver usbfs
[ 4.722868] usbcore: registered new interface driver hub
[ 4.728785] usbcore: registered new device driver usb
Mounting Temporary Directory (/tmp)...
[ 4.749212] usbcore: registered new interface driver ftdi_sio
[ 4.755020] usbserial: USB Serial support registered for FTDI USB Serial Device
[ OK ] Started Forward Password Requests to Wall Directory Watch.
[ OK ] Reached target Paths.
[ OK ] Listening on Journal Socket (/dev/log).
[ OK ] Created slice system-getty.slice.
[ OK ] Listening on udev Kernel Socket.
Starting udev Coldplug all Devices...
[ OK ] Created slice User and Session Slice.
[ OK ] Listening on Process Core Dump Socket.
Starting Journal Service...
[ OK ] Reached target Slices.
[ OK ] Listening on Network Service Netlink Socket.
[ OK ] Created slice system-serial\x2dgetty.slice.
[ OK ] Started Journal Service.
[ OK ] Started Load Kernel Modules.
[ OK ] Mounted Kernel Debug File System.
[ OK ] Mounted POSIX Message Queue File System.
[ OK ] Started Create list of required sta…vice nodes for the current kernel.
[ OK ] Started Remount Root and Kernel File Systems.
[ OK ] Mounted Temporary Directory (/tmp).
Starting Create Static Device Nodes in /dev...
Mounting Kernel Configuration File System...
Starting Apply Kernel Variables...
Starting Flush Journal to Persistent Storage...
[ OK ] Started Create Static Device Nodes in /dev.
[ OK ] Mounted Kernel Configuration File System.
[ OK ] Started Apply Kernel Variables.
[ 5.583375] systemd-journald[106]: Received request to flush runtime journal from PID 1
Starting udev Kernel Device Manager...
[ OK ] Reached target Local File Systems (Pre).
Mounting /media/ram...
[ OK ] Reached target Containers.
Mounting /var/volatile...
[ OK ] Started udev Kernel Device Manager.
[ OK ] Started Flush Journal to Persistent Storage.
[ OK ] Mounted /media/ram.
[ OK ] Mounted /var/volatile.
Starting Load/Save Random Seed...
[ OK ] Reached target Local File Systems.
Starting Create Volatile Files and Directories...
[ OK ] Started Load/Save Random Seed.
[ 5.941047] omap-rproc 58820000.ipu: ignoring dependency for device, assuming no driver
[ 5.992893] omap-rproc 58820000.ipu: ignoring dependency for device, assuming no driver
[ 6.042606] omap-rproc 58820000.ipu: assigned reserved memory node ipu1-memory@9d000000
[ OK ] Found device /dev/ttyS2.
[ 6.105337] remoteproc remoteproc0: 58820000.ipu is available
[ OK ] Started Create Volatile Files and Directories.
Starting Update UTMP about System Boot/Shutdown...
[ 6.157033] omap-rproc 55020000.ipu: ignoring dependency for device, assuming no driver
Starting Network Service...
[ 6.201717] omap-rproc 55020000.ipu: ignoring dependency for device, assuming no driver
Starting Network Time Synchronization...
[ 6.226820] omap-rproc 55020000.ipu: assigned reserved memory node ipu2-memory@95800000
[ OK ] Started udev Coldplug all Devices.
[ 6.239299] remoteproc remoteproc1: 55020000.ipu is available
[ 6.281360] omap-rproc 40800000.dsp: ignoring dependency for device, assuming no driver
[ OK ] Started Update UTMP about System Boot/Shutdow[ 6.304501] omap-rproc 40800000.dsp: ignoring dependency for device, assuming no driver
n.
[ 6.352470] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@99000000
[ 6.361522] remoteproc remoteproc2: 40800000.dsp is available
[ 6.384840] omap-rproc 41000000.dsp: ignoring dependency for device, assuming no driver
[ 6.400556] omap-rproc 41000000.dsp: ignoring dependency for device, assuming no driver
[ 6.416789] omap-rproc 41000000.dsp: assigned reserved memory node dsp2-memory@9f000000
[ 6.425308] remoteproc remoteproc3: 41000000.dsp is available
[ 6.511841] palmas-rtc 48070000.i2c:tps659038@58:tps659038_rtc: rtc core: registered 48070000.i2c:tps659038@58:tps659038_rtc as rtc1
[ 6.891461] omap_rtc 48838000.rtc: registered as rtc2
[ 6.899609] Driver for 1-wire Dallas network protocol.
[ 6.912203] remoteproc remoteproc1: powering up 55020000.ipu
[ 6.917943] remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3747220
[ 6.926271] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
[ 6.977675] remoteproc remoteproc0: powering up 58820000.ipu
[ 6.983371] remoteproc remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 6726740
[ 7.010839] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[ 7.017845] virtio_rpmsg_bus virtio0: rpmsg host is online
[ 7.024273] remoteproc remoteproc1: registered virtio0 (type 7)
[ 7.030574] remoteproc remoteproc1: remote processor 55020000.ipu is now up
[ 7.038084] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x65
[ 7.045642] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x66
[ 7.064089] virtio_rpmsg_bus virtio1: rpmsg host is online
[ 7.076344] remoteproc remoteproc0: registered virtio1 (type 7)
[ 7.082296] remoteproc remoteproc0: remote processor 58820000.ipu is now up
[ 7.158409] at24 0-0050: 4096 byte 24c32 EEPROM, writable, 1 bytes/write
[ 7.185447] omap_hdq 480b2000.1w: OMAP HDQ Hardware Rev 0.:. Driver in Interrupt mode
[ 7.226539] virtio_rpmsg_bus virtio1: creating channel rpmsg-proto addr 0x3d
[ 7.243788] virtio_rpmsg_bus virtio1: msg received with no recipient
[ 7.253200] tlv320aic3x-codec 0-0018: Linked as a consumer to regulator.3
[ 7.261156] tlv320aic3x-codec 0-0018: Linked as a consumer to regulator.4
[ 7.372207] ov5640 2-003c: 2-003c supply DOVDD not found, using dummy regulator
[ 7.386084] ov5640 2-003c: Linked as a consumer to regulator.0
[ 7.391975] ov5640 2-003c: 2-003c supply DVDD not found, using dummy regulator
[ 7.400288] ov5640 2-003c: 2-003c supply AVDD not found, using dummy regulator
[ 7.408385] ov5640 2-003c: ov5640_init_slave_id: client->addr= 3c
[ 7.416019] w1_master_driver w1_bus_master1: Attaching one wire slave 01.000000000000 crc 3d
[ 7.431775] w1_master_driver w1_bus_master1: Family 1 for 01.000000000000.3d is not registered.
[ OK ] Started Network Time Synchronization.
[ OK ] Reached target System Initialization.
[ OK ] Listening on RPCbind Server Activation Socket.
[ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket.
[ 7.582720] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[ 7.590476] net eth1: initializing cpsw version 1.15 (0)
Starting Reboot and dump vmcore via kexec...
[ 7.605431] omap-des 480a5000.des: will run requests pump with realtime priority
[ 7.739887] Micrel KSZ9031 Gigabit PHY 48485000.mdio:02: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:02, irq=POLL)
[ 7.758390] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 7.767323] net eth0: initializing cpsw version 1.15 (0)
[ 7.827684] phy phy-4a084000.phy.3: Linked as a consumer to regulator.23
[ 7.838220] phy phy-4a085000.phy.4: Linked as a consumer to regulator.23
[ OK ] Listening on dropbear.socket.
[ 7.847124] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[ 7.857185] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[ OK ] Started Daily Cleanup of Temporary Directorie[ 7.866261] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
s.
[ 7.922433] Micrel KSZ9031 Gigabit PHY 48485000.mdio:01: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:01, irq=POLL)
[ 7.943552] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 7.985577] vpe 489d0000.vpe: Device registered as /dev/video0
[ 8.077066] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[ 8.087269] omap-aes 4b500000.aes: will run requests pump with realtime priority
[ 8.101428] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[ 8.107421] omap-aes 4b700000.aes: will run requests pump with realtime priority
[ OK ] Listening on D-Bus System Message Bus Socket.[ 8.166757] omap-hdmi-audio omap-hdmi-audio.0.auto: snd-soc-dummy-dai <-> 58040000.encoder mapping ok
[ OK ] Reached target Sockets.
[ 8.182219] omap-hdmi-audio omap-hdmi-audio.0.auto: ASoC: no DMI vendor name!
[ OK ] Reached target Basic System.
[ 8.243859] virtio_rpmsg_bus virtio1: msg received with no recipient
[ 8.322923] [drm] Initialized pvr 1.17.4948957 20110701 for 56000000.gpu on minor 1
[ OK ] Started Periodic Command Scheduler.
Starting TI MultiCore Tools Daemon...
Starting TI IPC Daemon...
[ OK ] Started Job spooling tools.
[ 8.608802] ahci 4a140000.sata: controller can't do 64bit DMA, forcing 32bit
[ 8.616232] ahci 4a140000.sata: forcing port_map 0x0 -> 0x1
[ 8.623582] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[ 8.632301] ahci 4a140000.sata: flags: ncq sntf pm led clo only pmp pio slum part ccc apst
[ 8.643142] asoc-simple-card sound0: tlv320aic3x-hifi <-> 48468000.mcasp mapping ok
Starting RPC Bind Service...
[ 8.652433] asoc-simple-card sound0: ASoC: no DMI vendor name!
Starting Print notice about GPLv3 packages...
[ 8.683802] scsi host0: ahci
[ 8.687059] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 80
[ OK ] Started D-Bus System Message Bus.
Starting Login Service...
Starting uim-sysfs.service...
[ OK ] Reached target System Time Synchronized.
[ OK ] Started Daily rotation of log files.
[ OK ] Reached target Timers.
[ OK ] Started Network Service.
[ 8.883613] vip 48990000.vip: loading firmware vpdma-1b8.bin
Starting Network Name Resolution...
Starting Wait for Network to be Configured...
[ 9.015406] vip 48990000.vip: VPDMA firmware loaded
[ 9.021100] vin3a: Port A: Using subdev ov5640 2-003c for capture
[ 9.027849] vin3a-0: device registered as video1
[ 9.031957] ata1: SATA link down (SStatus 0 SControl 300)
[ 9.068123] remoteproc remoteproc3: powering up 41000000.dsp
[ 9.073817] remoteproc remoteproc3: Booting fw image dra7-dsp2-fw.xe66, size 20481364
[ 9.093599] remoteproc remoteproc2: powering up 40800000.dsp
[ 9.113728] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 20481364
[ 9.135622] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0
[ 9.141511] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0
[ 9.147935] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[ 9.153834] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[ 9.257165] virtio_rpmsg_bus virtio1: msg received with no recipient
[ 9.265591] virtio_rpmsg_bus virtio2: rpmsg host is online
[ 9.271737] remoteproc remoteproc3: registered virtio2 (type 7)
[ 9.351720] remoteproc remoteproc3: remote processor 41000000.dsp is now up
[ 9.458050] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3d
[ 9.523601] virtio_rpmsg_bus virtio3: rpmsg host is online
[ 9.534728] remoteproc remoteproc2: registered virtio3 (type 7)
[ OK ] Started Login Service.
[ OK ] Started Network Name Resolution.
[ OK ] Started Reboot and dump vmcore via kexec.
[ OK ] Started TI MultiCore Tools Daemon.
[ OK ] Started TI IPC Daemon.
[ OK ] Started RPC Bind Se[ 9.578866] remoteproc remoteproc2: remote processor 40800000.dsp is now up
rvice.
[ 9.719176] virtio_rpmsg_bus virtio3: creating channel rpmsg-proto addr 0x3d
[ 10.248858] virtio_rpmsg_bus virtio1: msg received with no recipient
[ 11.070048] dwc3 48890000.usb: Failed to get clk 'ref': -2
[ 11.088584] rpmsg_rpc virtio0.rpmsg-rpc.-1.101: probing service dce-callback with src 1024 dst 101
[ 11.097917] NET: Registered protocol family 45
[ 11.098835] dwc3 488d0000.usb: Failed to get clk 'ref': -2
[ OK ] Started uim-sysfs.service.
[ 11.117845] rpmsg_rpc virtio0.rpmsg-rpc.-1.102: probing service rpmsg-dce with src 1025 dst 102
[ 11.118181] rpmsg_rpc virtio0.rpmsg-rpc.-1.101: published functions = 4
[ 11.197896] rpmsg_rpc virtio0.rpmsg-rpc.-1.102: published functions = 9
[ 11.268470] Unable to handle kernel NULL pointer dereference at virtual address 0000001c
[ 11.290303] remoteproc remoteproc4: 4b234000.pru is available
[ 11.299818] pgd = a5537d37
[ 11.302804] [0000001c] *pgd=acffd003, *pmd=00000000
[ 11.322149] Internal error: Oops: 206 [#1] PREEMPT SMP ARM
[ 11.327667] Modules linked in: pru_rproc(+) irq_pruss_intc pruss rpmsg_proto rpmsg_rpc dwc3 udc_core ti_vip snd_soc_simple_card ahci_platform snd_soc_simple_card_utils libahci_platform libahci pvrsrvkm(O) snd_soc_omap_hdmi omap_aes_driver libata pruss_soc_bus ti_vpe omap_wdt omap_sham phy_omap_usb2 ti_sc omap_des ti_csc ov5640 des_generic ti_vpdma snd_soc_tlv320aic3x at24 omap_hdq v4l2_fwnode crypto_engine omap_crypto dwc3_omap wire extcon_palmas rtc_omap rtc_palmas omap_remoteproc virtio_rpmsg_bus remoteproc sch_fq_codel uio_module_drv(O) uio ftdi_sio usbserial usbcore usb_common jailhouse(O) gdbserverproxy(O) cryptodev(O) cmemk(O)
[ 11.327947] pru-rproc 4b234000.pru: PRU rproc node pru@4b234000 probed successfully
[ 11.384102] CPU: 0 PID: 718 Comm: v4l_id Tainted: G O 4.19.59-g5f8c1c6121 #11
[ 11.384106] Hardware name: Generic DRA74X (Flattened Device Tree)
[ 11.384118] PC is at __v4l2_ctrl_s_ctrl_int64+0x10/0x5c
[ 11.384130] LR is at ov5640_set_fmt+0x1a0/0x288 [ov5640]
[ 11.384137] pc : [<c07c34c0>] lr : [<bf1abfa4>] psr: 600f0013
[ 11.423254] sp : ec5fdb70 ip : ec5fdb90 fp : ec5fdb8c
[ 11.428503] r10: 00000004 r9 : 00000000 r8 : 0000001e
[ 11.433749] r7 : 00000000 r6 : ed693c44 r5 : 00000000 r4 : 00000000
[ 11.440300] r3 : 00000000 r2 : 0501bd00 r1 : 00000000 r0 : 00000000
[ 11.441493] remoteproc remoteproc5: 4b238000.pru is available
[ 11.446852] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
[ 11.446857] Control: 30c5387d Table: ad6b0880 DAC: fffffffd
[ 11.446863] Process v4l_id (pid: 718, stack limit = 0x4f6a3e88)
[ 11.446867] Stack: (0xec5fdb70 to 0xec5fe000)
[ 11.446872] db60: 00000000 00000000 ed693c44 ed693d8c
[ 11.446878] db80: ec5fdbb4 ec5fdb90 bf1abfa4 c07c34bc ec426040 bf339000 c1204c48 bf339400
[ 11.454604] pru-rproc 4b238000.pru: PRU rproc node pru@4b238000 probed successfully
[ 11.459801] dba0: 00000000 00000000 ec5fdc4c ec5fdbb8 bf3354d8 bf1abe10 ec5fdbdc ec5fdbc8
[ 11.459806] dbc0: c030226c c0300f30 ffefe8e8 00000001 00000000 00000780 00000438 00002006
[ 11.459811] dbe0: 00000001 00000008 00010001 00000002 00000000 00000000 00000000 00000000
[ 11.459819] dc00: 00000000 ec5fdc10 c0215168 c0215028 c1066e2c 00000014 c0321f48 00000000
[ 11.466911] remoteproc remoteproc6: 4b2b4000.pru is available
[ 11.471522] dc20: 00000001 a9166ef0 ec426040 c1204c48 00000000 ecd3f000 ed6a43c0 00000000
[ 11.476695] pru-rproc 4b2b4000.pru: PRU rproc node pru@4b2b4000 probed successfully
[ 11.484096] dc40: ec5fdd54 ec5fdc50 bf33579c bf335320 00000081 ec5fdd04 00000002 a9166ef0
[ 11.493271] remoteproc remoteproc7: 4b2b8000.pru is available
[ 11.499987] dc60: ec5fdd3c ecd3f000 00000081 006200ca ec52a750 b6e4e000 ecdee400 00000000
[ 11.499992] dc80: ec5fdd6c ec5fdc90 c02f915c c02f7a74 000000a0 c1204c48 ec5fdcb4 a9166ef0
[ 11.499996] dca0: c02ba800 a00f0013 ffffffff ec5fdcfc ec5fdd98 ec5fc000 ec5fdd34 ec5fdcc8
[ 11.500001] dcc0: c0201970 c021512c bf339200 00000001 ec5fc000 bf339200 ed9c77c0 bf339200
[ 11.500008] dce0: ee80dc00 ed9c77c0 ec5fdd98 00000000 ed9c77c0 bf339200 ec5fdd14 ec5fdd08
[ 11.509436] pru-rproc 4b2b8000.pru: PRU rproc node pru@4b2b8000 probed successfully
[ 11.516422] dd00: ec5fdd1c ec5fdd10 c07b2a38 c07b29a8 ec5fdd34 ec5fdd20 c07bb128 c0a13090
[ 11.516426] dd20: edbe0780 ed6a43c0 ec5fdd54 ec5fdd38 ec5fdd54 a9166ef0 ecedaca4 ed6a43c0
[ 11.516431] dd40: 00000000 ecd3f000 ec5fdd74 ec5fdd58 bf3359a0 bf335778 ecf94000 bf335924
[ 11.516438] dd60: ed6a43c0 ecf940f0 ec5fdd94 ec5fdd78 c07b2fe0 bf335930 c0c80048 c1204c48
[ 11.649976] dd80: ed9c77c0 ece75470 ec5fddc4 ec5fdd98 c0359060 c07b2f68 00000000 a9166ef0
[ 11.658185] dda0: ed6a43c0 ece75470 00000000 00020000 ed6a43c8 c0358fac ec5fddec ec5fddc8
[ 11.666397] ddc0: c03509c4 c0358fb8 ec5fde90 00000000 00000000 00020000 ee4023b8 ed6a43c0
[ 11.674607] dde0: ec5fddfc ec5fddf0 c0351ed0 c03508b4 ec5fde8c ec5fde00 c036369c c0351ea8
[ 11.682816] de00: c0324130 c0219ba0 00000000 200f0013 c0ddac38 00080000 ffffe000 04600000
[ 11.691026] de20: 0000075f ffefe000 00000041 c1204c48 00000002 00000000 ed6a43c0 00000000
[ 11.699238] de40: 00000002 ece75470 edb05510 ec898c38 00000000 00000000 00000000 a9166ef0
[ 11.707447] de60: 00000000 c1204c48 c1204c48 ec5fde90 ec5fdf50 00000001 ec5fc000 00000142
[ 11.715656] de80: ec5fdf44 ec5fde90 c0365580 c03633f0 edb05510 ec898c38 ebcda8fb 00000006
[ 11.723866] dea0: ecdd2015 c027eab0 00000000 ee6d8000 ece75470 00000101 00000002 00000658
[ 11.732076] dec0: 00000000 00000000 00000000 ec5fded0 ec5fdf04 00000003 ed66c500 ed66c518
[ 11.740288] dee0: 00000000 00000400 ed66c540 00000020 ec5fdf34 ec5fdf00 c0373e5c c0a13038
[ 11.748499] df00: ecdd2000 00000000 00000001 00000002 ffffff9c ffffff9c ecdd2000 a9166ef0
[ 11.756708] df20: ec5fc000 00000003 c1204c48 ffffff9c ecdd2000 fffff000 ec5fdf94 ec5fdf48
[ 11.764917] df40: c03521cc c0365510 c02411fc c0a1319c 00020000 ec5f0000 00000004 00000100
[ 11.773127] df60: 00000001 a9166ef0 00000008 b6f1c968 00417f38 00000000 00000142 c0201204
[ 11.781336] df80: ec5fc000 00000142 ec5fdfa4 ec5fdf98 c0352288 c0352068 00000000 ec5fdfa8
[ 11.789548] dfa0: c0201000 c0352280 b6f1c968 00417f38 ffffff9c bed52f2c 00020000 00000000
[ 11.797757] dfc0: b6f1c968 00417f38 00000000 00000142 bed52e34 00000000 00417f38 00000000
[ 11.805966] dfe0: b6e7922c bed52c30 00405b59 b6e62680 600f0010 ffffff9c 00000000 00000000
[ 11.814173] Backtrace:
[ 11.816640] [<c07c34b0>] (__v4l2_ctrl_s_ctrl_int64) from [<bf1abfa4>] (ov5640_set_fmt+0x1a0/0x288 [ov5640])
[ 11.826423] r7:ed693d8c r6:ed693c44 r5:00000000 r4:00000000
[ 11.832121] [<bf1abe04>] (ov5640_set_fmt [ov5640]) from [<bf3354d8>] (vip_init_port+0x1c4/0x458 [ti_vip])
[ 11.841727] r9:00000000 r8:00000000 r7:bf339400 r6:c1204c48 r5:bf339000 r4:ec426040
[ 11.849514] [<bf335314>] (vip_init_port [ti_vip]) from [<bf33579c>] (vip_init_stream+0x30/0x1b8 [ti_vip])
[ 11.859119] r9:00000000 r8:ed6a43c0 r7:ecd3f000 r6:00000000 r5:c1204c48 r4:ec426040
[ 11.866902] [<bf33576c>] (vip_init_stream [ti_vip]) from [<bf3359a0>] (vip_open+0x7c/0xac [ti_vip])
[ 11.875984] r7:ecd3f000 r6:00000000 r5:ed6a43c0 r4:ecedaca4
[ 11.881673] [<bf335924>] (vip_open [ti_vip]) from [<c07b2fe0>] (v4l2_open+0x84/0x110)
[ 11.889535] r7:ecf940f0 r6:ed6a43c0 r5:bf335924 r4:ecf94000
[ 11.895220] [<c07b2f5c>] (v4l2_open) from [<c0359060>] (chrdev_open+0xb4/0x19c)
[ 11.902557] r7:ece75470 r6:ed9c77c0 r5:c1204c48 r4:c0c80048
[ 11.908241] [<c0358fac>] (chrdev_open) from [<c03509c4>] (do_dentry_open+0x11c/0x3c0)
[ 11.916103] r9:c0358fac r8:ed6a43c8 r7:00020000 r6:00000000 r5:ece75470 r4:ed6a43c0
[ 11.923877] [<c03508a8>] (do_dentry_open) from [<c0351ed0>] (vfs_open+0x34/0x38)
[ 11.931301] r9:ed6a43c0 r8:ee4023b8 r7:00020000 r6:00000000 r5:00000000 r4:ec5fde90
[ 11.939077] [<c0351e9c>] (vfs_open) from [<c036369c>] (path_openat+0x2b8/0x1114)
[ 11.946507] [<c03633e4>] (path_openat) from [<c0365580>] (do_filp_open+0x7c/0xe4)
[ 11.954020] r10:00000142 r9:ec5fc000 r8:00000001 r7:ec5fdf50 r6:ec5fde90 r5:c1204c48
[ 11.961878] r4:c1204c48
[ 11.964422] [<c0365504>] (do_filp_open) from [<c03521cc>] (do_sys_open+0x170/0x1f4)
[ 11.972108] r8:fffff000 r7:ecdd2000 r6:ffffff9c r5:c1204c48 r4:00000003
[ 11.978836] [<c035205c>] (do_sys_open) from [<c0352288>] (sys_openat+0x14/0x18)
[ 11.986174] r10:00000142 r9:ec5fc000 r8:c0201204 r7:00000142 r6:00000000 r5:00417f38
[ 11.994033] r4:b6f1c968
[ 11.996578] [<c0352274>] (sys_openat) from [<c0201000>] (ret_fast_syscall+0x0/0x4c)
[ 12.004263] Exception stack(0xec5fdfa8 to 0xec5fdff0)
[ 12.009335] dfa0: b6f1c968 00417f38 ffffff9c bed52f2c 00020000 00000000
[ 12.017545] dfc0: b6f1c968 00417f38 00000000 00000142 bed52e34 00000000 00417f38 00000000
[ 12.025752] dfe0: b6e7922c bed52c30 00405b59 b6e62680
[ 12.030823] Code: e1a0c00d e92dd8f0 e24cb004 e1a07003 (e1d031dc)
[ 12.072625] ---[ end trace ae3e54dd5ff30d07 ]---
[ 12.119390] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[ 12.131380] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[ 12.153294] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x0000000002010010
[ 12.175837] xhci-hcd xhci-hcd.1.auto: irq 179, io mem 0x48890000
[ 12.186668] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
[ 12.197576] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 12.207876] usb usb1: Product: xHCI Host Controller
[ 12.214453] usb usb1: Manufacturer: Linux 4.19.59-g5f8c1c6121 xhci-hcd
[ 12.222420] usb usb1: SerialNumber: xhci-hcd.1.auto
[ 12.229793] hub 1-0:1.0: USB hub found
[ 12.234421] hub 1-0:1.0: 1 port detected
[ 12.239838] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[ 12.246043] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[ 12.254061] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[ 12.264782] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 12.273962] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
[ 12.282558] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 12.290597] usb usb2: Product: xHCI Host Controller
[ 12.295911] usb usb2: Manufacturer: Linux 4.19.59-g5f8c1c6121 xhci-hcd
[ 12.302713] usb usb2: SerialNumber: xhci-hcd.1.auto
[ 12.312160] hub 2-0:1.0: USB hub found
[ 12.317390] hub 2-0:1.0: 1 port detected
[ 12.605463] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[ 12.785975] usb 1-1: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00
[ 12.798274] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=1
[ 12.806611] usb 1-1: SerialNumber: E3000079FEB7
[ 12.872898] hub 1-1:1.0: USB hub found
[ 12.877215] hub 1-1:1.0: 4 ports detected
[ 12.936810] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
[ 12.976023] usb 2-1: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00
[ 12.984612] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 13.032932] hub 2-1:1.0: USB hub found
[ 13.037967] hub 2-1:1.0: 4 ports detected
[ 13.255434] usb 1-1.3: new low-speed USB device number 3 using xhci-hcd
[ 13.401115] usb 1-1.3: New USB device found, idVendor=413c, idProduct=2003, bcdDevice= 3.01
[ 13.409752] usb 1-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 13.418582] usb 1-1.3: Product: Dell USB Keyboard
[ 13.423482] usb 1-1.3: Manufacturer: Dell
[ 13.500565] input: Dell Dell USB Keyboard as /devices/platform/44000000.ocp/48880000.omap_dwc3_1/48890000.usb/xhci-hcd.1.auto/usb1/1-1/1-1.3/1-1.3:1.0/0003:413C:2003.0001/input/input0
[ 13.588023] hid-generic 0003:413C:2003.0001: input: USB HID v1.10 Keyboard [Dell Dell USB Keyboard] on usb-xhci-hcd.1.auto-1.3/input0
[ 13.601544] usbcore: registered new interface driver usbhid
[ 13.609241] usbhid: USB HID core driver
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
autoconf
bash-dev
bash
bc
binutils-dev
binutils
bison-dev
bison
cifs-utils
cpio
cpp-symlinks
cpp
dosfstools
elfutils-dev
elfutils
findutils
g++-symlinks
g++
gawk
gcc-symlinks
gcc
gdb
gdbc6x
gdbserver
gettext
glmark2
gstreamer1.0-libav
gzip
hidapi
libasm1
libbfd
libcairo-perf-utils
libdw1
libelf1
libgdbm-compat4
libgdbm-dev
libgdbm6
libgettextlib
libgettextsrc
libgmp10
libidn2-0
libmavconn
libmpc3
libmpfr6
libreadline-dev
libreadline7
libunistring2
m4-dev
m4
make
mavlink
mavros-extras
mavros-msgs
mavros
nettle
parted
pdm-anomaly-detection
socketcan-interface
swig-dev
swig
which
If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution. This can be done using
the opkg remove command. i.e.:
opkg remove <package>
Where <package> is the name printed in the list above
NOTE: If the package is a dependency of another package you
will be notified of the dependent packages. You should
use the --force-removal-of-dependent-packages option to
also remove the dependent packages as well
***************************************************************
***************************************************************
Starting Save/Restore Sound Card State...
[ OK ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
Starting rc.pvr.service...
[ OK ] Created slice system-systemd\x2dfsck.slice.
[ 15.365810] PVR_K: UM DDK-(4948957) and KM DDK-(4948957) match. [ OK ]
Starting File System Check on /dev/mmcblk0p1...
Starting File System Check on /dev/mmcblk1p1...
[ OK ] Reached target Network.
Starting Enable and configure wl18xx bluetooth stack...
Starting Lightning Fast Webserver With Light System Requirements...
[ OK ] Started Redis In-Memory Data Store.
Starting Permit User Sessions...
Starting Simple Network Management Protocol (SNMP) Daemon....
[ OK ] Reached target Host and Network Name Lookups.
[ OK ] Started NFS status monitor for NFSv2/3 locking..
Starting Avahi mDNS/DNS-SD Stack...
[ OK ] Started Print notice about GPLv3 packages.
[ OK ] Started Save/Restore Sound Card State.
[ OK ] Started rc.pvr.service.
[ OK ] Started Enable and configure wl18xx bluetooth stack.
[ OK ] Started Permit User Sessions.
[ OK ] Started Serial Getty on ttyS2.
[ OK ] Started Getty on tty1.
[ OK ] Reached target Login Prompts.
Starting Synchronize System and HW clocks...
Starting weston.service...
[ OK ] Reached target Sound Card.
[ OK ] Started File System Check on /dev/mmcblk0p1.
Mounting /run/media/mmcblk0p1...
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[ OK ] Started File System Check on /dev/mmcblk1p1.
[ OK ] Started weston.service.
[ OK ] Started Lightning Fast Webserver With Light System Requirements.
Starting Matrix GUI...
Starting telnetd.service...
Mounting /run/media/mmcblk1p1...
[ OK ] Started telnetd.service.
[ 15.941483] EXT4-fs (mmcblk1p1): mounted filesystem with ordered data mode. Opts: (null)
[ OK ] Started Matrix GUI.
[ OK ] Mounted /run/media/mmcblk0p1.
[ OK ] Mounted /run/media/mmcblk1p1.
[ OK ] Started Avahi mDNS/DNS-SD Stack.
Starting thttpd.service...
[ OK ] Started thttpd.service.
[ 17.159025] l4per_cm:clk:00d0:0: failed to disable
[ OK ] Started Simple Network Management Protocol (SNMP) Daemon..
_____ _____ _ _
| _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
| | _| .'| . | . | | __| _| . | | | -_| _| _|
|__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
|___| |___|
Arago Project http://arago-project.org am57xx-evm ttyS2
Arago 2019.07 am57xx-evm ttyS2
am57xx-evm login: root
root@am57xx-evm:~# cd ..
root@am57xx-evm:/home# cd ..
root@am57xx-evm:/# sudo dmesg | grep ov5640
[ 7.372084] ov5640 2-003c: GPIO lookup for consumer powerdown
[ 7.372091] ov5640 2-003c: using device tree for GPIO lookup
[ 7.372105] of_get_named_gpiod_flags: can't parse 'powerdown-gpios' property of node '/ocp/i2c@48060000/ov5640@3C[0]'
[ 7.372116] of_get_named_gpiod_flags: can't parse 'powerdown-gpio' property of node '/ocp/i2c@48060000/ov5640@3C[0]'
[ 7.372122] ov5640 2-003c: using lookup tables for GPIO lookup
[ 7.372127] ov5640 2-003c: No GPIO consumer powerdown found
[ 7.372133] ov5640 2-003c: GPIO lookup for consumer reset
[ 7.372137] ov5640 2-003c: using device tree for GPIO lookup
[ 7.372147] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/i2c@48060000/ov5640@3C[0]'
[ 7.372156] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/i2c@48060000/ov5640@3C[0]'
[ 7.372162] ov5640 2-003c: using lookup tables for GPIO lookup
[ 7.372167] ov5640 2-003c: No GPIO consumer reset found
[ 7.372207] ov5640 2-003c: 2-003c supply DOVDD not found, using dummy regulator
[ 7.386084] ov5640 2-003c: Linked as a consumer to regulator.0
[ 7.391975] ov5640 2-003c: 2-003c supply DVDD not found, using dummy regulator
[ 7.400288] ov5640 2-003c: 2-003c supply AVDD not found, using dummy regulator
[ 7.408385] ov5640 2-003c: ov5640_init_slave_id: client->addr= 3c
[ 9.021100] vin3a: Port A: Using subdev ov5640 2-003c for capture
[ 11.327667] Modules linked in: pru_rproc(+) irq_pruss_intc pruss rpmsg_proto rpmsg_rpc dwc3 udc_core ti_vip snd_soc_simple_card ahci_platform snd_soc_simple_card_utils libahci_platform libahci pvrsrvkm(O) snd_soc_omap_hdmi omap_aes_driver libata pruss_soc_bus ti_vpe omap_wdt omap_sham phy_omap_usb2 ti_sc omap_des ti_csc ov5640 des_generic ti_vpdma snd_soc_tlv320aic3x at24 omap_hdq v4l2_fwnode crypto_engine omap_crypto dwc3_omap wire extcon_palmas rtc_omap rtc_palmas omap_remoteproc virtio_rpmsg_bus remoteproc sch_fq_codel uio_module_drv(O) uio ftdi_sio usbserial usbcore usb_common jailhouse(O) gdbserverproxy(O) cryptodev(O) cmemk(O)
[ 11.384130] LR is at ov5640_set_fmt+0x1a0/0x288 [ov5640]
[ 11.816640] [<c07c34b0>] (__v4l2_ctrl_s_ctrl_int64) from [<bf1abfa4>] (ov5640_set_fmt+0x1a0/0x288 [ov5640])
[ 11.832121] [<bf1abe04>] (ov5640_set_fmt [ov5640]) from [<bf3354d8>] (vip_init_port+0x1c4/0x458 [ti_vip])
root@am57xx-evm:/# sudo dmesg | grep vip
[ 8.883613] vip 48990000.vip: loading firmware vpdma-1b8.bin
[ 9.015406] vip 48990000.vip: VPDMA firmware loaded
[ 11.327667] Modules linked in: pru_rproc(+) irq_pruss_intc pruss rpmsg_proto rpmsg_rpc dwc3 udc_core ti_vip snd_soc_simple_card ahci_platform snd_soc_simple_card_utils libahci_platform libahci pvrsrvkm(O) snd_soc_omap_hdmi omap_aes_driver libata pruss_soc_bus ti_vpe omap_wdt omap_sham phy_omap_usb2 ti_sc omap_des ti_csc ov5640 des_generic ti_vpdma snd_soc_tlv320aic3x at24 omap_hdq v4l2_fwnode crypto_engine omap_crypto dwc3_omap wire extcon_palmas rtc_omap rtc_palmas omap_remoteproc virtio_rpmsg_bus remoteproc sch_fq_codel uio_module_drv(O) uio ftdi_sio usbserial usbcore usb_common jailhouse(O) gdbserverproxy(O) cryptodev(O) cmemk(O)
[ 11.832121] [<bf1abe04>] (ov5640_set_fmt [ov5640]) from [<bf3354d8>] (vip_init_port+0x1c4/0x458 [ti_vip])
[ 11.849514] [<bf335314>] (vip_init_port [ti_vip]) from [<bf33579c>] (vip_init_stream+0x30/0x1b8 [ti_vip])
[ 11.866902] [<bf33576c>] (vip_init_stream [ti_vip]) from [<bf3359a0>] (vip_open+0x7c/0xac [ti_vip])
[ 11.881673] [<bf335924>] (vip_open [ti_vip]) from [<c07b2fe0>] (v4l2_open+0x84/0x110)
root@am57xx-evm:/# sudo dmesg | grep vpe
[ 7.857185] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[ 7.985577] vpe 489d0000.vpe: Device registered as /dev/video0
[ 11.327667] Modules linked in: pru_rproc(+) irq_pruss_intc pruss rpmsg_proto rpmsg_rpc dwc3 udc_core ti_vip snd_soc_simple_card ahci_platform snd_soc_simple_card_utils libahci_platform libahci pvrsrvkm(O) snd_soc_omap_hdmi omap_aes_driver libata pruss_soc_bus ti_vpe omap_wdt omap_sham phy_omap_usb2 ti_sc omap_des ti_csc ov5640 des_generic ti_vpdma snd_soc_tlv320aic3x at24 omap_hdq v4l2_fwnode crypto_engine omap_crypto dwc3_omap wire extcon_palmas rtc_omap rtc_palmas omap_remoteproc virtio_rpmsg_bus remoteproc sch_fq_codel uio_module_drv(O) uio ftdi_sio usbserial usbcore usb_common jailhouse(O) gdbserverproxy(O) cryptodev(O) cmemk(O)
root@am57xx-evm:/# sudo dmesg | grep video
[ 0.602968] videodev: Linux video capture interface: v2.00
[ 7.985577] vpe 489d0000.vpe: Device registered as /dev/video0
[ 9.027849] vin3a-0: device registered as video1
root@am57xx-evm:/# lsmod 0v5640
Usage: lsmod
root@am57xx-evm:/# lsmod
Module Size Used by
usbhid 24576 0
xhci_plat_hcd 16384 0
xhci_hcd 143360 1 xhci_plat_hcd
pru_rproc 20480 0
irq_pruss_intc 16384 1 pru_rproc
pruss 16384 1 pru_rproc
rpmsg_proto 16384 0
rpmsg_rpc 32768 0
dwc3 73728 0
udc_core 28672 1 dwc3
ti_vip 49152 1
snd_soc_simple_card 16384 0
ahci_platform 16384 0
snd_soc_simple_card_utils 16384 1 snd_soc_simple_card
libahci_platform 20480 1 ahci_platform
libahci 36864 2 ahci_platform,libahci_platform
pvrsrvkm 401408 2
snd_soc_omap_hdmi 16384 0
omap_aes_driver 24576 0
libata 208896 3 ahci_platform,libahci_platform,libahci
pruss_soc_bus 16384 0
ti_vpe 28672 0
omap_wdt 16384 0
omap_sham 28672 0
phy_omap_usb2 16384 3
ti_sc 36864 2 ti_vpe,ti_vip
omap_des 20480 0
ti_csc 16384 2 ti_vpe,ti_vip
ov5640 28672 1
des_generic 28672 1 omap_des
ti_vpdma 24576 2 ti_vpe,ti_vip
snd_soc_tlv320aic3x 57344 1
at24 20480 0
omap_hdq 16384 0
v4l2_fwnode 20480 2 ov5640,ti_vip
crypto_engine 16384 2 omap_des,omap_aes_driver
omap_crypto 16384 2 omap_des,omap_aes_driver
dwc3_omap 16384 0
wire 32768 1 omap_hdq
extcon_palmas 16384 0
rtc_omap 20480 0
rtc_palmas 16384 1
omap_remoteproc 20480 0
virtio_rpmsg_bus 20480 0
remoteproc 49152 4 pru_rproc,rpmsg_rpc,omap_remoteproc,rpmsg_proto
sch_fq_codel 20480 3
uio_module_drv 16384 0
uio 20480 1 uio_module_drv
ftdi_sio 40960 0
usbserial 36864 1 ftdi_sio
usbcore 217088 5 usbhid,ftdi_sio,usbserial,xhci_plat_hcd,xhci_hcd
usb_common 16384 3 udc_core,usbcore,dwc3
jailhouse 32768 0
gdbserverproxy 16384 0
cryptodev 49152 0
cmemk 45056 2
I am getting video1 in /dev/video* but i want to change the frame formats and colour space things.
Could you give me suggestions.
Is this right driver inplace of FPGA taken OV5640 or else any other driver i want to take because so many registers are there in ov5640?
In v4l2 capture frame rate, color space, and 16-bit data and 1080p30fps how to read video data where to change the formats?
Thanking you sir,
Regards,
Ramachandra
