AM5726: Regarding initialization of DSP1 & DSP2

Hi Sasaki-san,

1. The hardware as such does not have any limitations w.r.t boot order between DSP1 and DSP2.

2. How are you loading the DSPs? Are you using some debugger?

regards

Suman

Hi Suman-san,

Thank you for the information.

Suman Anna said:

How are you loading the DSPs? Are you using some debugger?

The ARM0 Project file contains the binary images of DSP1 and DSP2, which are memcpy in the main of ARM0 after booting from the SD card.
The initialization of each core is as follows.

1) ARM0
-Board_init (BOARD_INIT_UNLOCK_MMR | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO)
-Interrupt Xbar setting
・ RGMII setting
・ DSP1 / DSP2 initialization
・ Task generation, IPC setting
2) DSP1
・ Board_init (0) ・ ・ ・ UART is not initialized at this point.
-UART_init_bin (new addition)
・ Task generation, IPC setting
3) DSP2
・ Task generation, IPC setting

Best regards,
Sasaki

Hi Sasaki-san,

Sh.Sasaki said:

They cannot boot the device if they set DSP2 first and then DSP1 in that order.

Can you check what error they are facing when they set DSP2 and then DSP1?

Sh.Sasaki said:

 Is it possible to initialize and load DSP1 and DSP2 at the same time (parallel)?

Can you please elaborate more on this and what is the use case here?

Regards,
Parth

Hi Parth-san,

Thank you for your support.

Parth Nagpal said:

Can you check what error they are facing when they set DSP2 and then DSP1?

When the customer boots in the order of ARM0-> DSP2-> DSP1 using the emulator, the IPC cannot be initialized as shown below.
They guess the situation is where the device is waiting at Ipc_start

If they boot in the order ARM0-> DSP1-> DSP2, Ipc_ start will end normally.

Since it is the same Terminal situation when booting from the SD card, they think that it is looping in Ipc_start.

Parth Nagpal said:

Can you please elaborate more on this and what is the use case here?

Currently ARM1 will be unused, so they will boot both DSP cores from ARM0.
In doing so, they want to reduce the boot time of their devices as much as possible.
They are wondering if it would be possible to reduce the boot time by booting two DSP cores from the two tasks of ARM0.

Attach the customer's ARM0 program and memory map.

#define ENTRY_ADDRESS_DSP1           0xA0000000
#define ADDRESS_DSP1_IODELAY         0x40400000
#define ENTRY_ADDRESS_DSP2           0xA4000000

#define  CM_DSP1_CLKSTCTRL                              0x4A005400
#define  CM_DSP1_DSP_CLKCTRL                            0x4A005420
#define  RM_DSP1_RSTCTRL                                0x4AE06410
#define  RM_DSP1_RSTST                                  0x4AE06414
#define  CTRL_CORE_CONTROL_DSP1_RST_VECT                0x4A00255C

#define  CM_DSP2_CLKSTCTRL                              0x4A005600
#define  CM_DSP2_DSP_CLKCTRL                            0x4A005620
#define  RM_DSP2_RSTCTRL                                0x4AE07B10
#define  RM_DSP2_RSTST                                  0x4AE07B14
#define  CTRL_CORE_CONTROL_DSP2_RST_VECT                0x4A002560

         /* ========== Release DSP1 reset ========== */
         addr1 = ENTRY_ADDRESS_DSP1;
         IOREG32(CTRL_CORE_CONTROL_DSP1_RST_VECT,0) = 0x02000000 | (addr1 >> 10);
         IOREG32(RM_DSP1_RSTCTRL,0) = 0x3;
         IOREG32(CM_DSP1_CLKSTCTRL,0) = 0x2;
         IOREG32(CM_DSP1_DSP_CLKCTRL,0) = 0x1;
         while( (IOREG32(CM_DSP1_CLKSTCTRL,0) & 0x100) != 0x100 );
         IOREG32(RM_DSP1_RSTCTRL,0) = 0x1;
         while( (IOREG32(RM_DSP1_RSTST,0) & 0x2) != 0x2 );
         memcpy( (void *)(addr1), (void *)dsp1_data, dsp1_size );
         memcpy( (void *)(ADDRESS_DSP1_IODELAY), (void *)io_delay_data, io_delay_size ); //DSP1 uses UART, so it uses OCMC_RAM2
         Cache_wbInv((void *)(addr1), dsp1_size, Cache_Type_ALL, TRUE);
         IOREG32(RM_DSP1_RSTCTRL,0) = 0x0;
         while( (IOREG32(RM_DSP1_RSTST,0) & 0x3) != 0x3 );
         while( (IOREG32(CM_DSP1_DSP_CLKCTRL,0) & 0x30000) != 0x0 );

         /* ========== Release DSP2 reset ========== */
for (i = 0; i < 100000; i++) {
                   addr2 = ENTRY_ADDRESS_DSP2;
                   IOREG32(CTRL_CORE_CONTROL_DSP2_RST_VECT,0) = 0x02000000 | (addr2 >> 10);
         }
         IOREG32(RM_DSP2_RSTCTRL,0) = 0x3;
         IOREG32(CM_DSP2_CLKSTCTRL,0) = 0x2;
         IOREG32(CM_DSP2_DSP_CLKCTRL,0) = 0x1;
         while( (IOREG32(CM_DSP2_CLKSTCTRL,0) & 0x100) != 0x100 );
         IOREG32(RM_DSP2_RSTCTRL,0) = 0x1;
         while( (IOREG32(RM_DSP2_RSTST,0) & 0x2) != 0x2 );
         memcpy( (void *)(addr2), (void *)dsp2_data, dsp2_size );
         Cache_wbInv((void *)(addr2), dsp2_size, Cache_Type_ALL, TRUE);
         IOREG32(RM_DSP2_RSTCTRL,0) = 0x0;
         while( (IOREG32(RM_DSP2_RSTST,0) & 0x3) != 0x3 );
         while( (IOREG32(CM_DSP2_DSP_CLKCTRL,0) & 0x30000) != 0x0 );

The memory maps for DSP1 and DSP2 are as follows:
  L2SRAM                00800000   00040000  00000000  00040000  RW X
  OCMC_RAM1             40300000   00080000  00000000  00080000  RW X
  OCMC_RAM2             40400000   00100000  00002540  000fdac0  RW X
  OCMC_RAM3             40500000   00100000  00000000  00100000  RW X
  DDR3_HOST             80000000   20000000  00000000  20000000  RW X
  DDR3_DSP1             a0000000   00100000  00041924  000be6dc  RW X
  DDR3_DSP1_WORK        a0100000   03f00000  00ed2326  0302dcda  RW X
  DDR3_DSP2             a4000000   04000000  00000000  04000000  RW X
  DDR3_IPC              a8000000   04000000  04000000  00000000  RW X

  L2SRAM                00800000   00040000  00000000  00040000  RW X
  OCMC_RAM1             40300000   00080000  00000000  00080000  RW X
  OCMC_RAM2             40400000   00100000  00000000  00100000  RW X
  OCMC_RAM3             40500000   00100000  00000000  00100000  RW X
  DDR3_HOST             80000000   20000000  00000000  20000000  RW X
  DDR3_DSP1             a0000000   04000000  00000000  04000000  RW X
  DDR3_DSP2             a4000000   00100000  0004e5ea  000b1a16  RW X
  DDR3_DSP2_WORK        a4100000   03f00000  00138e0e  03dc71f2  RW X
  DDR3_IPC              a8000000   04000000  04000000  00000000  RW X

Best regards,
Sasaki

Hi Parth-san,

Do you have any information?

Best regards,
Sasaki

Hi Parth-san,

Could you give us some comment?

Best regard,
Sasaki

Hi Parth-san

Thank you for the reply.

Parth Nagpal said:

It shows that both the DSPs can be loaded independently. I am looking for some example that loads DSP2 and then DSP1. 

Can you please share what example are you trying to load to the DSPs?

The customer's source code is below.

#define ENTRY_ADDRESS_DSP1 0xA0000000
#define ADDRESS_DSP1_IODELAY 0x40400000
#define ENTRY_ADDRESS_DSP2 0xA4000000

#define CM_DSP1_CLKSTCTRL 0x4A005400
#define CM_DSP1_DSP_CLKCTRL 0x4A005420
#define RM_DSP1_RSTCTRL 0x4AE06410
#define RM_DSP1_RSTST 0x4AE06414
#define CTRL_CORE_CONTROL_DSP1_RST_VECT 0x4A00255C

#define CM_DSP2_CLKSTCTRL 0x4A005600
#define CM_DSP2_DSP_CLKCTRL 0x4A005620
#define RM_DSP2_RSTCTRL 0x4AE07B10
#define RM_DSP2_RSTST 0x4AE07B14
#define CTRL_CORE_CONTROL_DSP2_RST_VECT 0x4A002560

/* ========== Release DSP1 reset ========== */
addr1 = ENTRY_ADDRESS_DSP1;
IOREG32(CTRL_CORE_CONTROL_DSP1_RST_VECT,0) = 0x02000000 | (addr1 >> 10);
IOREG32(RM_DSP1_RSTCTRL,0) = 0x3;
IOREG32(CM_DSP1_CLKSTCTRL,0) = 0x2;
IOREG32(CM_DSP1_DSP_CLKCTRL,0) = 0x1;
while( (IOREG32(CM_DSP1_CLKSTCTRL,0) & 0x100) != 0x100 );
IOREG32(RM_DSP1_RSTCTRL,0) = 0x1;
while( (IOREG32(RM_DSP1_RSTST,0) & 0x2) != 0x2 );
memcpy( (void *)(addr1), (void *)dsp1_data, dsp1_size );
memcpy( (void *)(ADDRESS_DSP1_IODELAY), (void *)io_delay_data, io_delay_size ); //DSP1 uses UART, so it uses OCMC_RAM2
Cache_wbInv((void *)(addr1), dsp1_size, Cache_Type_ALL, TRUE);
IOREG32(RM_DSP1_RSTCTRL,0) = 0x0;
while( (IOREG32(RM_DSP1_RSTST,0) & 0x3) != 0x3 );
while( (IOREG32(CM_DSP1_DSP_CLKCTRL,0) & 0x30000) != 0x0 );

/* ========== Release DSP2 reset ========== */
for (i = 0; i < 100000; i++) {
addr2 = ENTRY_ADDRESS_DSP2;
IOREG32(CTRL_CORE_CONTROL_DSP2_RST_VECT,0) = 0x02000000 | (addr2 >> 10);
}
IOREG32(RM_DSP2_RSTCTRL,0) = 0x3;
IOREG32(CM_DSP2_CLKSTCTRL,0) = 0x2;
IOREG32(CM_DSP2_DSP_CLKCTRL,0) = 0x1;
while( (IOREG32(CM_DSP2_CLKSTCTRL,0) & 0x100) != 0x100 );
IOREG32(RM_DSP2_RSTCTRL,0) = 0x1;
while( (IOREG32(RM_DSP2_RSTST,0) & 0x2) != 0x2 );
memcpy( (void *)(addr2), (void *)dsp2_data, dsp2_size );
Cache_wbInv((void *)(addr2), dsp2_size, Cache_Type_ALL, TRUE);
IOREG32(RM_DSP2_RSTCTRL,0) = 0x0;
while( (IOREG32(RM_DSP2_RSTST,0) & 0x3) != 0x3 );
while( (IOREG32(CM_DSP2_DSP_CLKCTRL,0) & 0x30000) != 0x0 );

The memory maps for DSP1 and DSP2 are as follows:
L2SRAM 00800000 00040000 00000000 00040000 RW X
OCMC_RAM1 40300000 00080000 00000000 00080000 RW X
OCMC_RAM2 40400000 00100000 00002540 000fdac0 RW X
OCMC_RAM3 40500000 00100000 00000000 00100000 RW X
DDR3_HOST 80000000 20000000 00000000 20000000 RW X
DDR3_DSP1 a0000000 00100000 00041924 000be6dc RW X
DDR3_DSP1_WORK a0100000 03f00000 00ed2326 0302dcda RW X
DDR3_DSP2 a4000000 04000000 00000000 04000000 RW X
DDR3_IPC a8000000 04000000 04000000 00000000 RW X

L2SRAM 00800000 00040000 00000000 00040000 RW X
OCMC_RAM1 40300000 00080000 00000000 00080000 RW X
OCMC_RAM2 40400000 00100000 00000000 00100000 RW X
OCMC_RAM3 40500000 00100000 00000000 00100000 RW X
DDR3_HOST 80000000 20000000 00000000 20000000 RW X
DDR3_DSP1 a0000000 04000000 00000000 04000000 RW X
DDR3_DSP2 a4000000 00100000 0004e5ea 000b1a16 RW X
DDR3_DSP2_WORK a4100000 03f00000 00138e0e 03dc71f2 RW X
DDR3_IPC a8000000 04000000 04000000 00000000 RW X

Parth Nagpal said:

You can load both the cores using two tasks, but I don't think that would reduce boot time much, unless both the tasks are running on different cores, because a single core can handle only one task at any given point of time.

I agree with your opinion.
Please let me know if there is a way to change the customer source code mentioned above to reduce the startup time.

Best regards,
Sasaki

Hi Parth-san,

The DSP boot order issue has been resolved. Thank you for your answer.

Best regards,
Sasaki