• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 492 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AM5728: MMC2 DDR mode timing

AM5728: Hold time for the timing of MMC2 DDR mode

Kanae
Guru 10165 points
Part Number: AM5728


Hi Support Team,


It was answered in the forum that the calculation method of the hold time
for the timing of MMC2 DDR mode of AM5728 can be obtained from the following formula.

Hold time is calculated as
(Pulse width) + ((delay from host CLK -> device) + (delay from device DAT -> host)) - (trace length mismatch between CLK - DAT).
Your trace length should satisfy this equation such that min hold time = 1.8 ns.

Q. Is it correct that "pulse width" in this equation refers to the pulse width of CLK?
  Since the clock used is 48MHz, the pulse width is 1/48MHz/2=10.4ns.
  If we apply this to the formula for hold time, is it correct to expect that it is easy to maintain
  more than 1.8ns if the delay and wiring error between host and device is in the order of ps?

Best regards,
Kanae

  • 0
    TI__Genius 10180 points

    Kanae,

    Looking at this again, the term "(Pulse Width)" actually does not apply to the hold time in DDR mode.  The hold time should be calculated as ((delay from host CLK -> device) + (delay from device DAT -> host)) - (trace length mismatch between CLK - DAT).  

    Pulse width is only in effect when the data is launched and captured off of different edges.  An example is Legacy SDR mode where data is launched off of falling edge, and captured on rising edge.

    Best regards,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Guru 10165 points


    Hi Shiou Mei,

    Thank you for your reply.
    I will share the above information from you with my customer.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    Guru 10165 points


    Hi Shiou Mei,

    Please let me check just to be sure.
    Can I understand that the following delays are the transmission delays ( routing delays )
    in the CLK/DATA line of the actual board?

    - Delay from host CLK -> device
    - Delay from device DAT -> host

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Genius 10180 points

    Kanae,

    The delay from CLK -> device is only taking into account the routing delays, but the delay from device DAT -> host should also take into account the output delay from the device. 

    A better equation might be ((Component output delay + (min delay from host CLK -> device) + (min delay from device DAT -> host)) - (trace length mismatch between CLK - DAT)).  In this case the (delay from host CLK -> device) and (delay from device DAT -> host) are only referring to the routing delays, and the (Component output delay) is the min delay time the device takes to output the data.

    Best Regards,

    Shiou Mei