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AM6442: Powering with the single PMIC solution

Daisuke Maeda
Guru 20425 points

Part Number: AM6442
Other Parts Discussed in Thread: TPS745

Our customer is designing a prototype board with the AM6442 SR1.0 and powering the AM6442 + DDR memory with the single PMIC solution. And I have a few questions about the powering.

The power connections are as follows.

The following application note was referenced for the single PMIC solution.

Powering the AM64xx With the LP8733xx PMIC
www.ti.com/.../slvaes0.pdf
Figure 1. Powering AM64x With LP8733xx │DDR4 Memory

Can the GPO2 pin on the LP873364 be directly connected to the EN pin on the TPS6282x and the EN pin on the TPS745?

The output low level voltage (VOL) of the GPO2 pin on the LP873364 is 0.4V (MAX), but the input low level threshold voltage (VL) of the EN pin on the TPS6282x is 0.4V (MAX), and the input low level threshold voltage (VEN(LO)) of the EN pin on the TPS745 is 0.3V (MAX).

The power-up/down sequence in the power connections is as follows.

The following document was referenced for the power-up/down sequence of the LP873364.

LP873364 Technical Reference Manual
www.ti.com/.../snvu810.pdf
Figure 3-1. LP873364 Power-up and Power Down Sequence

Can the power-down sequence of the LP873364 meet the power-down sequence of the AM64x requirements?

VDD_CORE on AM64x is not allowed to be ramped down before other power supply inputs.

Best regards,

Daisuke

  • 0
    Guru 20425 points

    Hi,

    For my first question, I understood that it is possible.

    > Can the GPO2 pin on the LP873364 be directly connected to the EN pin on the TPS6282x and the EN pin on the TPS745?

    e2e.ti.com/.../3953405

    Could you please answer for my second question?

    > Can the power-down sequence of the LP873364 meet the power-down sequence of the AM64x requirements?
    >
    > VDD_CORE on AM64x is not allowed to be ramped down before other power supply inputs.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 8275 points

    Hi Daisuke-san,

    Daisuke Maeda said:
    Can the power-down sequence of the LP873364 meet the power-down sequence of the AM64x requirements?

    I confirmed, yes it can.

    Daisuke Maeda said:
    VDD_CORE on AM64x is not allowed to be ramped down before other power supply inputs.

    I received this answer from the systems experts, and will be in an upcoming app note release, which is to address this issue:

    The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by the same source such that they ramp together when VDD_CORE is operating at 0.85V.

    Regards,

    Colin

  • 0 in reply to Colin Callaghan
    Guru 20425 points

    Hi Colin-san,

    Thank you for your reply.

    Best regards,

    Daisuke