A lot of HDVPSS functions (Deinterlacer, Scaler, noise filter, display, capture) are available through distributed OpenMax apis on Netra. Our concern is cache coherency issues among multiple processors that may arise by mixing codec engine apis and openmax apis.
Our DSP custom xDM codec sits smack in the middle in the media chain involving video m3 (IVAHD) and ducati (HDVPSS).
Video encoder/decoder running on IVAHD accelerators on netra is accessed from Linux Arm more readily and remotely as openmax components( but not through codec engine), via openmax server, which manages scheduling on video m3's accelerators ( codec engine runs locally on video m3, there is no codec server on video m3).
There is no codec engine remote API, that I know of to talk to the video encoder running on video arm m3 cpu.
In addition to skeletons and stubs, going both ways (RTOS and HLOS, both have skel & stubs) , distributed openmax also has callbacks. By design most openmax APIs are non blocking on HLOS like linux ( helps when you have to run upto 32 video encoder/decoders, not to context switch due to blocking call apis on HLOS like linux).
We need more clarification from TI as to which distributed processing approach ( Codec Engine / Distributed openmax) we have to use for the DSP on Netra.
This is just my 2 cents, I am still learning the DM8168. So please correct me if I am wrong.
RV