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TDA4VM: How to config DSS for BT656?

lemon liu
Prodigy 40 points

Part Number: TDA4VM

Hi,

We are using TDA4 for developing.

TDA4 SDK:  ti-processor-sdk-rtos-j721e-evm-08_00_00_12

We want to display CVBS video on LCD: TDA4 DSS vout0(BT656)->ADV7393(video encoder)->LCD(CVBS).

DSS can output bt656 format video, and adv7393 support 720*480(BT656) Input. 

Run run_app_multi_cam.sh on the board, A72 can get video from camera, but there is no display on LCD. There is output on VOUT0_PCLK and VOUT0_DATA2-DATA9, The clk frequency is 27M. LCD can display ADV7393  COLOR BAR test pattern.

I made the changes in vision_apps:

1. vision_apps\apps\basic_demos\app_tirtos\common\app_init.c: set LCD timing.

Refer to 8bit BT656 NTSC timing:

prm.timings.width = 720U;
prm.timings.height = 480U;
prm.timings.hFrontPorch = 20U;
prm.timings.hBackPorch = 3U;
prm.timings.hSyncLen = 276;
prm.timings.vFrontPorch = 19U;
prm.timings.vBackPorch = 3U;
prm.timings.vSyncLen = 0U;
prm.timings.pixelClock = 27000000ULL;
2. app_dss_defaults.c:  

// Enable BT656 and set scan format to interlaced.
vpParams.scanFmt = FVID2_SF_INTERLACED;
vpParams.dvoFormat = APP_DCTRL_DV_BT656_EMBSYNC;
3. app_display_module.h: modify display resolution
#define DISPLAY_WIDTH (720)
#define DISPLAY_HEIGHT (480)

So I have two questions:

1. Is the LCD timing configure correct? 

2. Is there anything else that needs to be changed in SDK?

  • 0
    TI__Guru**** 501085 points

    Hi,

    Well, the changes look fine to me. We just need to enable BT656 output and then interlaced mode. Could you first enable internal color bar of DSS and if it gets displayed correctly?

    Regards,

    Brijesh 

  • 0 in reply to Brijesh Jadav
    Prodigy 40 points

    Hi  Brijesh,

    After made blow changes, the video can display on LCD. But the color is abnormal, and the video scrolling on LCD.

    prm.timings.hFrontPorch = 18U;
    prm.timings.hBackPorch = 5U;
    prm.timings.hSyncLen = 267;
    prm.timings.vFrontPorch = 16U;
    prm.timings.vBackPorch = 2U;
    Use the test cases in TIOVX, the issue still exist.
    Test command: ./vx_app_conformance.out --filter=tivxHwaDisplay.*
    I think the LCD timing is still incorrect.
    Best regards,
    Chengzhi Liu
  • 0 in reply to lemon liu
    Prodigy 40 points

    Enable internal color bar of DSS, the issue still exist.

  • 0 in reply to lemon liu
    TI__Guru**** 501085 points

    Hi Chengzhi Liu,

    It seems your horizontal timing is correct, seems to be some issue in vertical timing. 

    Can you please read back SIZE_SCREEN, TIMING_H and TIMING_V register and share them?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 40 points

    Hi  Brijesh,

    You can see the value of registers below:

    [MCU2_0] 19.207663 s: CSL_DSS_VP2_CONFIG regaddr= 0x04aa0000, vaule=0x03500000
    [MCU2_0] 19.207715 s: CSL_DSS_VP2_CONTROL regaddr= 0x04aa0004, vaule=0x00000041
    [MCU2_0] 19.207748 s: CSL_DSS_VP2_TIMING_H regaddr= 0x04aa0054, vaule=0x0120050b
    [MCU2_0] 19.207780 s: CSL_DSS_VP2_TIMING_V regaddr= 0x04aa0058, vaule=0x01000201
    [MCU2_0] 19.207813 s: CSL_DSS_VP2_SIZE_SCREEN regaddr= 0x04aa0050, vaule=0x00ef02cf

    Best regards,

    Chengzhi Liu
  • 0 in reply to lemon liu
    TI__Guru**** 501085 points

    Hi Liu,

    When in BT656 mode, the meaning of the fields change slightly. 

    VFP = Vertical Blanking1 for ODD field

    VBP = Vertical Blanking2 for ODD field

    HFP = Vertical Blanking1 for EVEN field

    HBP = Vertical Blanking2 for EVEN field

    Now can you please rearrange your timing such that, vertical blanking is exactly 22 lines for both the fields and then use DELTA_LPP field in SIZE_SCREEN register to keep one field size one line higher than the other field size? 

     

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 40 points

    Hi  Brijesh,

    I set DELTA_LPP field in SIZE_SCREEN register and update LCD timing setting, but LCD still can't output normally.

    I have tried many combinations of vertical blanking lines,ex: (20,2),(19,3),(18,4),(16,6), but it doesn't work.

    drvVpParams.lcdOpTimingCfg.deltaLinesPerPanel = CSL_DSS_VP_LPP_DELTA_MINUSONE;

    Update LCD timing setting:
    prm.timings.hFrontPorch = 16U;
    prm.timings.hBackPorch = 6U;
    prm.timings.hSyncLen = 267;
    prm.timings.vFrontPorch = 15U;
    prm.timings.vBackPorch = 5U;
    prm.timings.vSyncLen = 0U;

    Best regards,

    Chengzhi Liu
  • 0 in reply to lemon liu
    Prodigy 40 points

    After changes the edge Polarity type,  LCD can output normally.

    vpParams.pixelClkPolarity = APP_DCTRL_EDGE_POL_FALLING;
  • 0 in reply to lemon liu
    TI__Guru**** 501085 points

    Thanks Liu, closing this ticket.