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video capture problems when test TVP5158 on dm6467

Other Parts Discussed in Thread: TVP5158

 

Hi.

     I am working on the hardware test on  the TI's dm6467 platform.  My custom board is tvp5158+dm6467. The tvp5158 portA is connected to dm6467 vpif0 .

     All  tests past  except that there is some problem with the video sequence captured,which is  described as follows:

      I found that Both the Y plane data and the UV plane data of  odd frames are incorrect ,while the even frames are ok,When I analyse the raw data in the buffer of vpif and display the images with matlab,   The images I get is included in the attachment for you to check.

(the odd frames is incorrect as above)


(the even frames is ok as above)

       I did the test under CCSv3.3 , setting tvp5158 as 1ch-D1 PAL bt.656 mode. My tvp5158 reg config is as follows:

       B0 = 0x00;

       B1 = 0x10;    

       B2 = 0x05;

       B6 = 0x1B;

       B7 = 0x14;

 

the key configure of the vpif is as follows:

    // set flied mode ,offset for line store is 720 pixes

    channel0->regs->IMG_LINE_OFFSET =720;

    channel0->regs->HSIZE_CFG   = ( 280 << 16 ) | ( 1440 << 0 );

    channel0->regs->VSIZE_CFG0  = (   1 << 16 ) | (   23 << 0 );

    channel0->regs->VSIZE_CFG1  = ( 311 << 16 ) | (  313 << 0 );

    channel0->regs->VSIZE_CFG2  = ( 336 << 16 ) | (  624 << 0 );

    channel0->regs->VSIZE_CFG3  = 625;

    // vpif ctl reg

    VPIF_CHCTRL0 = 0

        | ( 0 << 12 )           // Input Field mode

        | ( 0 << 10 )           // Interlaced Format

        | ( 0 << 9 )            // No Vertical Ancillary

        | ( 0 << 8 )            // No Horizontal Ancillary

        | ( 2 << 6 )            // [2] Interrupt on Bottom Field

        | ( 0 << 5 )            // FID top field

        | ( 0 << 4 )            // Raster

        | ( 1 << 3 )            // Y/C on same byte stream

        | ( 1 << 1 )            // FORMAT BT Video

        | ( 0 << 0 );           // Channel Disabled

  ------------------------------------------------------------------------------------

       Then I check the test code, and find the PLL config in EVMDM6467_startupGEL() function:

 

    // Setup PLL0 , (clock_mode, multiplier, post_div )

    EVMDM6467_enablePll0( OSCIN, 21, 0 );   // Setup Pll1 ( DSP @ 594 MHz )

    // Setup DDR2 , (clock_mode, multiplier, post_div )

    EVMDM6467_enablePll1( OSCIN, 21, 0 );   // Setup Pll2 ( DDR @ 297 MHz )

 

    When I change the PLL1 multiplier from 21 to 22, the problem has some changes, on the contrary,all the even frames become incorrect while all the odd frames are correct.

 

    -------------------------------------------------------------------------------------

 

    Who can help me and provide some details?

 

    Thank you very much!