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AM5728: Linux/AM5728: GPMC read fpga data issue

Part Number: AM5728
Other Parts Discussed in Thread: AM4378, , TEST

Dears,

We use gpmc interface to connect to fpga( use addr/data mux mode, and sync read/write ),  on am4378 ,we read/write data both ok, now we should change to am5728 platfrom,  then porting the gpmc config from am437x to am5728(configs are all same),   now, if we write 

the odd data to fpga , read back data is ok,   but when wirte even data and read the data back,  the D[0] bit is always 0,  it seems thant   lost D[0] bit.   please help me, urgent ,thanks

this is my test:

odd data is ok,  0x2a is addr ,  0x22 is  odd data:

root@am57xx-evm:/sys/class/misc/gpmc-fpga# echo 0x2a 0x22 > fpga_reg
root@am57xx-evm:/sys/class/misc/gpmc-fpga# cat fpga_reg
0x22
root@am57xx-evm:/sys/class/misc/gpmc-fpga#

root@am57xx-evm:/sys/class/misc/gpmc-fpga# echo 0x2a 0x44 > fpga_reg
root@am57xx-evm:/sys/class/misc/gpmc-fpga# cat fpga_reg
0x44
root@am57xx-evm:/sys/class/misc/gpmc-fpga#

even data  is error:0x2a is addr ,  0x23 is  even  data:

root@am57xx-evm:/sys/class/misc/gpmc-fpga# echo 0x2a 0x23 > fpga_reg                      ====> even data 
root@am57xx-evm:/sys/class/misc/gpmc-fpga# cat fpga_reg                                     
0x22                                                                                             ====>error data, D[0] bit is 0, so  0x23 change to 0x22
root@am57xx-evm:/sys/class/misc/gpmc-fpga#

root@am57xx-evm:/sys/class/misc/gpmc-fpga# echo 0x2a 0x33 > fpga_reg                      =====>evne data
root@am57xx-evm:/sys/class/misc/gpmc-fpga# cat fpga_reg
0x32                                                                                                                                   ====>error data, D[0] bit is 0, so  0x33 change to 0x32
root@am57xx-evm:/sys/class/misc/gpmc-fpga#

At the first time I guess the D[0] pin line is always pull down low , but after I write the even data to fpga , it can write the even data to fpga side, fpga  can recive the even data, then  I read the even data,  the fpga also can send even data to gpmc , but when to arm side , the  result is change to odd data, bit D[0] changed to 0.

below is my pin config and dts config file:

mayi_fpga_default: mayi_fpga_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ //gpmc_ad[15:0]-->gpmc_ad[15:0]--->fpga_ad[15:0];
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */


DRA7XX_CORE_IOPAD(0x3444, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_a1.gpmc_a17 */ // gpmc_a[11:1]-->gpmc_a[27:17]--->fpga_a[26:16];
DRA7XX_CORE_IOPAD(0x3448, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_a2.gpmc_a18 */
DRA7XX_CORE_IOPAD(0x344c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_a3.gpmc_a19 */
DRA7XX_CORE_IOPAD(0x3450, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_a4.gpmc_a20 */
DRA7XX_CORE_IOPAD(0x3454, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_a5.gpmc_a21 */
DRA7XX_CORE_IOPAD(0x3458, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* gpmc_a6.gpmc_a22 */

DRA7XX_CORE_IOPAD(0x34c0, PIN_OUTPUT | MUX_MODE0) /* gpmc_clk */
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */

 

&gpmc {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mayi_fpga_default>;

ranges = <0 0 0x08000000 0x04000000>; /* mayi fpga on CS0 space. Min partition = 128MB */
fpga@0,0 {
compatible = "mayi,gpmc-fpga";
reg = <0 0 0x04000000>;
bank-width = <2>;
gpmc,mux-add-data = <2>; //mux addr;


gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <70>;
gpmc,cs-wr-off-ns = <60>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <30>;
gpmc,we-off-ns = <60>;
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <70>;
gpmc,access-ns = <60>;
gpmc,rd-cycle-ns = <70>;
gpmc,wr-cycle-ns = <60>;

//gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <20>;
gpmc,cycle2cycle-samecsen = <10>;
gpmc,cycle2cycle-diffcsen = <0>;
gpmc,wr-access-ns = <60>; //?
gpmc,wr-data-mux-bus-ns = <30>;
gpmc,page-burst-access-ns = <10>;
};
};