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66AK2G12: Disabling DDR ECC

Koichiro Tashiro
Mastermind 22945 points
Part Number: 66AK2G12


Hi,

My customer is developing their system without using DDR ECC feature and wants to know how to disable EMIF ECC.
Customer refers evm gel file and found below description at line#2157.

	if(ECC_Enable == 0)
	{
		read_val = DDR3A_DATX8_4;				
		DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
	}

DDR3A_DATX8_4 register address is defined as 0x0232:92C0.

Here is complete gel file.
 evmk2g_arm.gel

On the other hand, TRM section 7.2.4.9 has below description.


https://www.tij.co.jp/jp/lit/ug/spruhy8i/spruhy8i.pdf?ts=1642486311432&ref_url=https%253A%252F%252Fwww.tij.co.jp%252Fproduct%252Fjp%252F66AK2G12%253FkeyMatch%253D66AK2G12%2526tisearch%253Dsearch-everything%2526usecase%253DGPN

And DDR_PHY_DX8GCR address is 0x0232:93C0.
There is no register mapped at 0x0232:92C0 in TRM register table.

I guess DDR3A_DATX8_4 in gel file and DDR_PHY_DX8GCR in TRM are the same register, but address is different.
Which one is correct address?

Thanks and regards,
Koichiro Tashiro



  • 0
    TI__Guru* 89485 points

    ECC should be disabled with EMIF_ECCCTL.ECC_EN bit, and the ECC byte lane is disabled with the register noted above.  It looks like there is a typo in the GEL, DDR3A_DATX8_4 is mapped to 0x023293C0

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 22945 points

    Hi James,

    Sorry for the delay.

    JJD said:
    It looks like there is a typo in the GEL, DDR3A_DATX8_4 is mapped to 0x023293C0


    The customer removed below lines from GEL, but it results in CCS hang-up and debugger is disconnected.

        if(ECC_Enable == 0)
    {
//            read_val = DDR3A_DATX8_4;                                                 
//            DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
    }

    DDR3A_DATX8_4 is mapped at 0x0232:92C0 in the GEL.
    Customer wonders the address in GEL file is valid.
    Could you double check this?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 22945 points

    Hi James,

    Customer found below comment in evmk2g_arm.gel file line#2175. 

    	// Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
	// If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
	// If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
	// If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
	// NOTE: Setup supports 64-bit by default,  ECC enable by default.

    If these comments are correct, DATX8_8 (offset 0x3C) is the register DDR_PHY_DX8GCR in TRM.
    And below GEL file line# 2157 is wrong.
    	if(ECC_Enable == 0)
	{
		read_val = DDR3A_DATX8_4;				
		DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
	}

    It should be like below (register name is changed to DATX8_8);
    	if(ECC_Enable == 0)
	{
		read_val = DDR3A_DATX8_8;				
		DDR3A_DATX8_8 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
	}


    Also line#2172 is also incorrect.
    	read_val = DDR3A_DATX8_8;				
	  DDR3A_DATX8_8 = read_val & 0xFFFFFFFE; //Disable BL8 byte lane - not present in K2G

    The register name should be "DATX8_4".
    	read_val = DDR3A_DATX8_4;				
	  DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable BL8 byte lane - not present in K2G


    Correct?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru* 89485 points

    Koichiro, these modification look like the right thing to do.  Is the customer having success with these changes?  If so, i can look into making these modifications in the GEL release for this device.

    Regards,

    James

  • 0 in reply to JJD
    TI__Mastermind 22945 points

    Hi James,

    Customer made below modifications in GEL and the updated GEL seems working fine.

                  if(ECC_Enable == 0)
              {
//                        read_val = DDR3A_DATX8_4;                                                 
//                        DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
                            read_val = DDR3A_DATX8_8;                                                 
                            DDR3A_DATX8_8 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
              }
              
//          read_val = DDR3A_DATX8_8;                                                 
//            DDR3A_DATX8_8 = read_val & 0xFFFFFFFE; //Disable BL8 byte lane - not present in K2G
              read_val = DDR3A_DATX8_4;                                                 
                DDR3A_DATX8_4 = read_val & 0xFFFFFFFE; //Disable BL8 byte lane - not present in K2G


    Could you confirm these changes are correct from K2G specification point of view?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru* 89485 points

    Yes, they do seem correct.  I will submit a change for the GEL

    Regards,

    James