AMIC110: PRU-ICSS EtherCAT Slave Controller Register (0x300 RX Error Counter)

Hideaki Matsumoto

Part Number: AMIC110

Hi,

My customer is developing EtherCAT module with AMIC110 and have a question about the counter value (0-7bit) of 0x300 (RX Error Counter) on EtherCAT Slave Controller register.

Is this counter value reset every link up or link down ?

When the cable is disconnected or broken externally during communication, they monitor this counter value, but zero is read every time.

Therefore, they’re guessing that this counter is reset every link up or link down.

Regards,

Hideaki

over 3 years ago

0 Dhaval Khandla over 3 years ago

TI__Mastermind 27924 points

Hideaki Matsumoto said:
counter value (0-7bit) of 0x300 (RX Error Counter)

0-7 bit tracks Invalid frame counter, not RX Error counter. Can you clarify whether the question is regarding Invalid frame counter or RX Error counter?

Reference for register description : https://software-dl.ti.com/processor-industrial-sw/esd/docs/indsw/EtherCAT_Slave/PRU_ICSS_EtherCAT_Slave_Controller_Register_List.html

If you are talking about bit 0-7, I did some testing with TwinCAT and following are the observations.

Testing with slave in INIT state : The counter does not reset on link break.
Testing with slave in OP state : The counter does reset. But a potential reason for this is that TwinCAT master writes to these counters and as mentioned in the register description for 0x300, these registers are cleared if any of the counters (0x300-0x30b) is written.

Regards
Dhaval Khandla

0 Hideaki Matsumoto over 3 years ago in reply to Dhaval Khandla

TI__Genius 9360 points

Hi, Dhaval,

Thank you for your reply.

> 0-7 bit tracks Invalid frame counter, not RX Error counter. Can you clarify whether the question is regarding Invalid frame counter or RX Error counter?

Yes, they're recognizing 0-7 bit tracks invalid frame counter.

Could you tell them what kind of test you did with TwinCAT ?

They tried to corrupt the data physically by making up the cable in order to generate invalid frame intentionally, but the counter doesn’t increase even if INIT state.

Thanks and regards,

Hideaki Matsumoto

0 Dhaval Khandla over 3 years ago in reply to Hideaki Matsumoto

TI__Mastermind 27924 points

Hideaki Matsumoto said:
Could you tell them what kind of test you did with TwinCAT ?

I tried updating the error counter from Memory browser in CCS, and saw that the register is not reset on link break.

Regards
Dhaval Khandla

0 Dhaval Khandla over 3 years ago in reply to Dhaval Khandla

TI__Mastermind 27924 points

Hideaki Matsumoto said:
They tried to corrupt the data physically by making up the cable in order to generate invalid frame intentionally, but the counter doesn’t increase even if INIT state.

Can you provide more details on this?

You can run at lower cycle times and increase the process data size and add CoE transactions. This increases probability of frame corruption during link break/RX_ER.

Regards
Dhaval Khandla

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AMIC110: PRU-ICSS EtherCAT Slave Controller Register (0x300 RX Error Counter)