Part Number: J721EXSOMXEVM
Hello,
We have J721e based board and one of the Ethernet switch port (configured as SGMII) has Mac-to-Mac connection to another ECU. I have enabled the port 1 (port 1 is configured as mac to mac) main_tirtos.c. With this change I built and loaded the ethernet firmware but i am getting following error -
=> =======================================================
CPSW Ethernet Firmware
=======================================================
CPSW_9G Test on MAIN NAVSS
Enet_open: cpsw9g: features: 0x00000002
Enet_open: cpsw9g: errata : 0x00000000
CpswMacPort_setSgmiiInterface: MAC 1: SERDES PLL is not locked
CpswMacPort_setSgmiiInterface: MAC 1: Failed to set SGMII interface: -9
CpswMacPort_open: MAC 1: failed to set Q/SGMII interface: -9
EnetMod_open: cpsw9g.macport1: Failed to open: -9
Cpsw_openPortLinkNoPhy: Port 1: Failed to open MAC: -9
Cpsw_handleLinkDown: Port 1: Link down
EnetMod_ioctl: cpsw9g.macport1: Module is not open
Cpsw_handleLinkDown: Port 1: Failed to disable MAC port: -1
Cpsw_ioctlInternal: Port 1: Failed to open port link: -9
EnetPer_ioctl: cpsw9g: Failed to do IOCTL cmd 0x01000102: -9
Enet_ioctl: cpsw9g: IOCTL 0x01000102 failed: -9
EnetMcm_enablePorts() failed to open MAC port: -9
PHY 0 is alive
PHY 4 is alive
PHY 5 is alive
PHY 8 is alive
PHY 10 is alive
PHY 12 is alive
ETHFW Version : 0.01.01
ETHFW Build Date: Mar 19, 2021
ETHFW Build Time: 15:33:31
ETHFW Commit SHA:
Host MAC address: 70:ff:76:1d:92:c2
IPC_echo_test (core : mcu2_0) .....
[NIMU_NDK] ENET has been started successfully
Remote demo device (core : mcu2_0) .....
CPSW NIMU application, IP address I/F 1: 192.168.1.203
EnetMod_ioctl: cpsw9g.macport3: Module is not open
EnetPer_ioctl: cpsw9g: Failed to do IOCTL cmd 0x01010501: -1
Enet_ioctl: cpsw9g: IOCTL 0x01010501 failed: -1
Assertion @ Line: 1333 in src/ip/cpsw/timeSync_cpsw.c: status == TIMESYNC_OK : failed !!!
My Serdes configuration in board_serdes_cfg.c for this SGMII port looks like below -
static Board_STATUS Board_CfgSgmii_0(void)
{
CSL_SerdesResult result;
CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
/* SGMII Config */
serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE0;
serdesLane0EnableParams.baseAddr = CSL_SERDES_16G0_BASE;
serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT;
serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
serdesLane0EnableParams.numLanes = 0x2;
serdesLane0EnableParams.laneMask = 0x3;
serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLane0EnableParams.phyInstanceNum = SERDES_LANE_SELECT_CPSW;
serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
serdesLane0EnableParams.laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;
serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
/* Select the IP type, IP instance num, Serdes Lane Number */
// Lane 0 /* Added */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
SGMII_LANE_NUM0);
// Lane 1
/* CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
SGMII_LANE_NUM1); */
result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.baseAddr,
serdesLane0EnableParams.refClock,
serdesLane0EnableParams.refClkSrc,
serdesLane0EnableParams.serdesInstance,
serdesLane0EnableParams.phyType);
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
/* Assert PHY reset and disable all lanes */
CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
/* Load the Serdes Config File */
result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
/* Return error if input params are invalid */
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
/* Common Lane Enable API for lane enable, pll enable etc */
laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
if (laneRetVal != 0)
{
return BOARD_FAIL;
}
return BOARD_SOK;
}
Please let me know how to debug this issue.
Thank you,
Satish
