I knew D0 and D1 are configurable as MOSI and MISO, but when in SPI bootmode, which pin of D0 and D1 is MISO and MOSI? is it configurable in SPI boot mode?
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I knew D0 and D1 are configurable as MOSI and MISO, but when in SPI bootmode, which pin of D0 and D1 is MISO and MOSI? is it configurable in SPI boot mode?
James,
seems you made mistake, on AM62-SK set boot mode to SPI , the config register shows D0 as MOSI.
spi config register:
Register description is not clear in AM62x TRM:
From AM335x TRM, detail description as below:
Boot mode register set tp SPI boot.
Hi Tony, you are correct i had this backwards
D0 is MOSI, DQ is MISO
However, the McSPI module doesn't perform boot. The OSPI module performs boot, even in SPI mode. The register that dictates the data direction is OSPI_DEV_INSTR_RD_CONFIG_REG.DATA_XFER_TYPE_EXT_MODE_FLD, which the ROM will set to 0x0 for SPI mode.
I will get this clarified in the documentation
Regards,
James
Tony, it is not configurable for boot. The ROM chooses D0 MOSI, D1 MISO and it cannot be changed when booting from OSPI boot. However, in your application, you can change the configuration for OSPI (configured in SPI mode) or McSPI if necessary.
What do you mean "DPE0/1 doesn't effect"?
Regards,
james