Part Number: DRA821U
Hello,
I am designing a DRA821U design with the TPS6594 PMIC utilizing the PDN-2 design. In my design, all the IO are 1.8V and not 3.3V. I am planning on having a buck converter that powers all the 1.8V IO rails except the 1.8V PLL rails (This will be on LDO4). In the datasheet for DRA821U it mentions in section 7.10.2.2 that the 1.8V rail is supposed to come up at time T1. In my design the 1.8V IO rails will come up slightly before (1.9ms) the 1.8V PLL rails (2ms-2.5ms). I didn't see any notes specifically stating if the 1.8V rails need to come up exactly together. All 1.8V rails in my design will come up before the CPU/CORE rails.
Thanks for your reply
