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OMAP 3530 SPI1 SOMI (Slave Out Master In ) not working

Murali Vemuri
Prodigy 80 points
Other Parts Discussed in Thread: SYSCONFIG

Hello there,

I found a few threads on this topic but none of them helped me exactly.

Let me describe my problem:

I modified the EVM kernel to support all my devices. (touch screen is no longer connected on SPI on my board). 

I have connected an SPI client on SPI1 of OMAP 3530 (CUS Package).

For absolute clarity, OMAP is the SPI master and my device is the Client/Slave.

When I send any data on SIMO (Master Out - Slave In) , I am able to write to the device, there by configuring certain parameters.

However my SOMI (Slave Out Master In) line does not seem to be working. 

The operation I am trying to do involves 8 bit write and 16 bit read from the slave. So, I am using the call spi_w8r16() .

As long as I did not set the MCSPI_CLK as INPUTENABLE in the PADCONF, all my read operations were 0x00. After I set the clock as INPUT ENABLE, all the read operations are returning as 0xFF.

However, using a 2-channel Oscilloscope, I dumped the clock and data, and found that the data as returned by my SPI slave is: 0xB001. 

This is the line that was enabling the MCSPI_CLK in pad conf: 

OMAP3_MUX(MCSPI1_CLK,OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT| OMAP_PIN_INPUT), 

When I try to read , this is my MCSPI register dump:

MCSPI REGISTER DUMP START************************

OMAP2_MCSPI_REVISION    : 21 

OMAP2_MCSPI_SYSCONFIG   : 15 

OMAP2_MCSPI_SYSSTATUS   : 1 

OMAP2_MCSPI_IRQSTATUS   : 7 

OMAP2_MCSPI_IRQENABLE   : 0 

OMAP2_MCSPI_WAKEUPENABLE: 1 

OMAP2_MCSPI_SYST        : 0 

OMAP2_MCSPI_MODULCTRL   : 1 

OMAP2_MCSPI_CHCONF0     : 1103f0 

OMAP2_MCSPI_CHSTAT0     : 7 

OMAP2_MCSPI_CHCTRL0     : 1 

OMAP2_MCSPI_TX0         : 0 

OMAP2_MCSPI_RX0         : ff 

OMAP2_MCSPI_XFER_LVL    : 0 

MCSPI REGISTER DUMP END**************************

 

Well... any suggestions as to what is going wrong here?

Thanks in advance.

Murali

  • 0
    Intellectual 895 points

    Hi Murali,

    The INPUTENABLE bit for SPI_CLK must always be set in master mode in OMAP as this signal is used for re-timing input when SPI port is configured as master.

    I did face a similar issue with SPI3 where the data read was always 0x00 but the actual data on SOMI line was different. For my case, the issue was solved by setting the INPUTENABLE bit for SPI_CLK pad. Also the MUX MODE was set to M4 for SOMI somewhere at kernel level which was creating issue while reading.

    For me, this issue was happening with my application at kernel level but I was able to read data through SPI3 at uboot level. When I compared the PADCONF settings for uboot and kernel, there was a difference. As of now, INPUTENABLE is set for all the SPI signals - CLK, CS, SOMI and SIMO in my code and this is working. I feel INPUTENABLE must be set for CLK (used as retiming input) and SOMI signal (which is an input). For CS and SIMO, this is redundant and should not affect the working as these signals are used as output.

    Also make sure that the MUX MODE is set properly for SIMO as you are seeing data on line but not able to read it properly.

     

    Vini

  • 0 in reply to Vini
    Prodigy 80 points

    Hello Vini & others,

    Thanks for the reply. 

    In my PAD conf, I enabled INPUT / OUTPUT on all 4 lines, (CS, CLK, SOMI & SIMO). 

    OMAP3_MUX(MCSPI1_CLK,OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT| OMAP_PIN_INPUT),         

    OMAP3_MUX(MCSPI1_SIMO,OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT| OMAP_PIN_INPUT),       

    OMAP3_MUX(MCSPI1_SOMI,OMAP_MUX_MODE0 | OMAP_PIN_INPUT| OMAP_PIN_OUTPUT),       

    OMAP3_MUX(MCSPI1_CS0,OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT | OMAP_PIN_INPUT),

     

    I also tried with changing the mode from MUX_MODE 0 to MUX_MODE 4. 

    As of now, the data read is still wrong.

    I am not sure if there is any other way of enabling the input on CLK or any other PIN. (As I mentioned, I am using OMAP 3530 & EVM kernel).

    please let me know if you have any other suggestions.

     

    Thanks & regards

    Murali

  • 0 in reply to Murali Vemuri
    Intellectual 895 points

    Hi Murali,

    MUX_MODE 0 only will work for SPI1. Sorry, if I created confusion. For me, MUX_MODE was wrongly set and thats why I just wanted you to confirm MUX_MODE setting.

    You can also verify the edge for SPI_CLK.

     

    Vini