Hi All,
I am trying to configure PORT8 as SGMII. The PHY on our custom board is connected to lane1 of serdes0.
Getting "SERDES PLL is not locked" error. CpswMacPort_setSgmiiInterface()::CSL_SGMII_getSerdesPLLLockStatus->CPSW_SGMII_STATUS_REG
The SDK used is 8.0.0.12.
I am attaching the changes i have done to configure PORT8 as sgmii.
Please review and help me.
Thanks,
Vishal
diff --git a/packages/ti/board/src/j721e_evm/board_ethernet_config.c b/packages/ti/board/src/j721e_evm/board_ethernet_config.c
index 575b2e2db..a473da8ab 100755
--- a/packages/ti/board/src/j721e_evm/board_ethernet_config.c
+++ b/packages/ti/board/src/j721e_evm/board_ethernet_config.c
@@ -711,11 +711,14 @@ Board_STATUS Board_ethConfigCpsw9g(void)
{
if ( 0U == portNum ||
2U == portNum ||
- 3U == portNum ||
- 7U == portNum )
+ 3U == portNum)
{
status = Board_cpsw9gEthConfig(portNum, RGMII);
}
+ else if (7U == portNum )
+ {
+ status = Board_cpsw9gEthConfig(portNum, SGMII);
+ }
else
{
if (1U == portNum)
diff --git a/packages/ti/board/src/j721e_evm/board_pinmux.c b/packages/ti/board/src/j721e_evm/board_pinmux.c
index 1593733bd..753e51976 100755
--- a/packages/ti/board/src/j721e_evm/board_pinmux.c
+++ b/packages/ti/board/src/j721e_evm/board_pinmux.c
@@ -420,7 +420,7 @@ Board_STATUS Board_pinmuxConfig (void)
if(gBoardPinmuxCfg.gesiExp == BOARD_PINMUX_GESI_CPSW)
{
/* Overwrite the ICSSG RGMII muc configurations with CPSW9G RGMII */
- Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9g,
+ Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gSgmii,
BOARD_SOC_DOMAIN_MAIN);
Board_pinmuxUpdate(gJ721E_WkupPinmuxDataGesiCpsw9g,
BOARD_SOC_DOMAIN_WKUP);
@@ -494,7 +494,7 @@ Board_STATUS Board_pinmuxConfigMain (void)
if(gBoardPinmuxCfg.gesiExp == BOARD_PINMUX_GESI_CPSW)
{
/* Overwrite the ICSSG RGMII muc configurations with CPSW9G RGMII */
- Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9g,
+ Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gSgmii,
BOARD_SOC_DOMAIN_MAIN);
}
}
diff --git a/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c b/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
index 82a54f54b..53d7d89e0 100644
--- a/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
+++ b/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c
@@ -342,7 +342,7 @@ uint32_t EnetBoard_getPhyAddr(Enet_Type enetType,
case ENET_MAC_PORT_8:
/* RGMII port */
- phyAddr = 15U;
+ phyAddr = 4U;
break;
case ENET_MAC_PORT_2:
@@ -384,7 +384,7 @@ uint32_t EnetBoard_getSgmiiPhyAddr(void)
{
/* Both Q/SGMII DB and GESI board use MAC port 2, so we can't use generic EnetBoard_getPhyAddr
* function */
- return 10U;
+ return 4U;
}
uint32_t EnetBoard_getRmiiPhyAddr(void)
@@ -405,7 +405,7 @@ void EnetBoard_setPhyConfigSgmii(Enet_MacPort portNum,
/* Override the ENET control set by board lib */
#if defined (SOC_J721E)
- EnetAppUtils_assert(portNum == ENET_MAC_PORT_2);
+// EnetAppUtils_assert(portNum == ENET_MAC_PORT_2);
enetType = ENET_CPSW_9G;
instId = 0U;
#elif defined (SOC_J7200)
@@ -626,8 +626,7 @@ void EnetBoard_setPhyConfig(Enet_Type enetType,
case ENET_CPSW_9G:
if ( ENET_MAC_PORT_1 == portNum ||
ENET_MAC_PORT_3 == portNum ||
- ENET_MAC_PORT_4 == portNum ||
- ENET_MAC_PORT_8 == portNum )
+ ENET_MAC_PORT_4 == portNum)
{
EnetBoard_setPhyConfigRgmii(enetType,
portNum,
@@ -635,14 +634,14 @@ void EnetBoard_setPhyConfig(Enet_Type enetType,
interface,
phyCfg);
}
- else
- {
- EnetBoard_setPhyConfigQsgmii(enetType,
- portNum,
- macCfg,
- interface,
- phyCfg);
- }
+ else if (ENET_MAC_PORT_8 == portNum)
+ {
+ ENETTRACE_ERR("#########MAC 8 condition\n");
+ EnetBoard_setPhyConfigSgmii(portNum,
+ macCfg,
+ interface,
+ phyCfg);
+ }
break;
default:
diff --git a/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c b/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c
index 0872fa03d..99c67eae3 100644
--- a/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c
+++ b/packages/ti/drv/enet/examples/utils/enet_board_j7xevm.c
@@ -243,16 +243,19 @@ static const EnetBoard_PortCfg gEnetGesiBoard_j721eEthPort[] =
.enetType = ENET_CPSW_9G,
.instId = 0U,
.macPort = ENET_MAC_PORT_8,
- .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
+ .mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },
.phyCfg =
{
- .phyAddr = 15U,
+ .phyAddr = 4U,
.isStrapped = false,
.skipExtendedCfg = false,
- .extendedCfg = &gEnetGesiBoard_dp83867PhyCfg,
- .extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg),
+ .extendedCfg = NULL,
+ .extendedCfgSize = 0U,
},
- .flags = ENET_BOARD_J7XEVM_CPSW9G_MDIO_MUX,
+ .flags = (ENET_BOARD_J7XEVM_CPSW9G_MDIO_MUX |
+ ENET_BOARD_J7XEVM_SERDES_SIERRA0_CLKS |
+ ENET_BOARD_J7XEVM_SERDES_SIERRA1_CLKS |
+ ENET_BOARD_J7XEVM_SERDES_TORRENT_CLKS),
},
{ /* "PRG0_RGMII1_B" */
.enetType = ENET_CPSW_9G,
@@ -754,6 +757,8 @@ static const EnetBoard_PortCfg *EnetBoard_getPortCfg(const EnetBoard_EthPort *et
#if defined(SOC_J721E)
if (ethPort->enetType == ENET_CPSW_9G)
{
+
+ EnetAppUtils_print("SGMII :::::::::::::::::::: Configuring port\n");
portCfg = EnetBoard_findPortCfg(ethPort,
gEnetGesiBoard_j721eEthPort,
ENETPHY_ARRAYSIZE(gEnetGesiBoard_j721eEthPort));
@@ -937,7 +942,7 @@ int32_t EnetBoard_setupPorts(EnetBoard_EthPort *ethPorts,
}
}
- EnetAppUtils_print("EnetBoard_setupPorts: %u of %u ports configurations found\n", hits, numEthPorts);
+ EnetAppUtils_print("SGMII:::::::::::::EnetBoard_setupPorts: %u of %u ports configurations found\n", hits, numEthPorts);
/* Set pinmux for either CPSW9G or ICSSG, they are mutually exclusive */
Board_pinmuxGetCfg(&pinmuxCfg);
@@ -1026,6 +1031,7 @@ int32_t EnetBoard_setupPorts(EnetBoard_EthPort *ethPorts,
/* QpENet QSGMII PHY init */
if ((ENET_NOT_ZERO(flags & ENET_BOARD_J7XEVM_QPENET_INIT)) && (qenetDetected))
{
+ EnetAppUtils_print("SGMII :::::::::::::::::::: qnetDetected\n");
EnetBoard_enetExpCfg();
}
