Hi，TI
I am using an AM5728 device and both the AM57x Schematic Checklist (Rev. B) and the TRM manual state that sysboot14 must be connected to VSS.
But unfortunately we didn't notice this requirement when we first designed, when sysboot14 was pulled high, we set the PCIe DPLL clock output to the ljcb_clk pin, which measured 104MHz. When sysboot14 is pulled low, it measures 100MHz.
I would like to know if this sysboot14 has any other effects besides this pcie DPLL frequency offset issue we have found so far?
