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C6748 SPI1 Flash Boot Intermittent

William Shaffer
Intellectual 335 points

Hello,
We are having some major issues booting from SPI1 Flash with the C6748.  What makes the problem frustrating is that sometimes it boots, sometimes it doesn't.  General Info:

DM6748
Silicon Revision 2.0
ROM ID: d800k006

I believe the problem lies in the latching of the boot mode pins at power on, but I don't know for sure...when the board boots, I can connect with the emulator and the boot mode is set to SPI 1 flash, but when the board does not boot, i connect and it says that the boot mode is I2C0 EEPROM (aka Bootmode[7..0] = 0000 0000), which seems to suggest that the core is released from reset before the 3.3v supply that controls the bootmode pins is up.  We have verified that the supply ramp up is correct, and it looks like the reset signal is released long after the voltage levels are correct.

Any suggestions and questions are welcome.
Thanks!

  • 0
    TI__Mastermind 27585 points

    Can you give a scope shot with a few of the bootpins (ones that should be '1') along with the RESETN and TRSTn signals? If you could the show the core and IO power rails on the scope shot too that would be helpful too.

    Also, can you try leaving the board powered and repeatedly resetting the chip? Does it ever read I2C0 EEPROM in that case, or does it latch the boot pins correctly in that case?

    Jeff

     

  • 0 in reply to jc-ti
    Intellectual 335 points

    Jeff,
    I will try to grab the screen shots tomorrow if you think it will help...right before the end of the day I tried to reset the board but it did not seem to relatch the boot mode; I2C0 EEPROM was always the boot mode...there are a few lines that are configurable with a dip switch, and even if i change the values, it always reports the boot mode that was latched when the board was powered on.

    That being said, I looked into it and noticed that a power on reset requires both the RESET and TRST lines to be pulled low together, while a warm reset requires just the RESET line is pulled low.  So does that mean that the reset line from the voltage supervisor should go to both the RESET and TRST lines?  At the moment it just goes to the RESET line.  If i jumper it so that the voltage supervisor is tied to both lines, the board will boot up correctly all the time. 

    Let me know what you think. Thanks.

  • 0 in reply to William Shaffer
    TI__Mastermind 27585 points

    You should have a pulldown on TRST, and you will need to remove the JTAG cable if you doing a warm reset and change the boot mode. Have you tried this?

    Jeff