DRA821U: SERDES0_REFCLK Termination when used as Input

Are there any external termination requirements on SERDES0_REFCLK_P/N signals when they are used as a clock input? The reference design uses these as an output and has 49.9ohm pull down resistors. Can/should these be removed in input clock mode? Is any other termination required when used in input clock mode?

Thanks,

Stuart