DM3x5 and unknown device ID

The 4th byte ID is a bit confusing. I am using rev1.4 silicon, but NOT samsung NAND.

If I use the "4th ID Byte in Legacy and Samsung Format" (sec 11.2.2.1.3 - TMS320DM355 ARM subsystem), would I define it as:

For the purpose of determining NAND block size and page size the information from the fourth byte is

considered as follows:

• Bits 5 and 4 determine the block size

– Bits 5,4 = 00: 64KB

– Bits 5,4 = 01: 128KB

– Bits 5,4 = 10: 256KB

– Bits 5,4 = 11: 512KB

• Bits 1 and 0 determine the page size

– Bits 1,0 = 00: 1KB

– Bits 1,0 = 01: 2KB

– Bits 1,0 = 10: 4KB

– Bits 1,0 = 11: 8KB

or this?

In silicon revision 1.4, the latest Samsung (manufacturer ID: 0xEC) 4th ID definition has been added which

is as follows:

• Bits 5 and 4 determine the block size

– Bits 5,4 = 00: 128KB

– Bits 5,4 = 10: 256KB

– Bits 5,4 = 01: 512KB

– Bits 5,4 = 11: 1024KB

• Bits 1 and 0 determine the page size

– Bits 1,0 = 00: 2KB

– Bits 1,0 = 01: 3KB

– Bits 1,0 = 10: 4KB

– Bits 1,0 = 11: reserved

Thanks

Jamie

The NAND we are connecting to is from Micron (Device ID = 0x2C) and returns 0x26 fourth byte.

According to the table, this would be block size = 256kB and page size = 4kB

However, the micron NAND part is block size = 512kB and page size = 4kB.

How will the RBL behave if it has the wrong info?

It looks likethe Micron device (ID = 0x2C) doesn't conform to the 4th byte format for obtaining the correct nand geometry.

In this case the solution to correctly supply the nand parameter to the RBL is to use the EERPOM.

See section 2.4.2 of

TMS320DM355/DM335 Migration Guide

http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=spraba1b&fileType=pdf

Just looking for some more clarification on this issue.

I have found many posts on similar topic, but I still have a couple questions.

1. The wiki page shows a flow chart about NAND boot and shows Method 5 as loading default paramters. However the DM355 datashest and errata only show the first 4 methods. Is this because the TMS320DM355 does not have (support) default NAND parameters?

2. The NAND I am using is not on the Device ID table, and the 4th byte (0x26) does not match the NAND parameters (512k block). Therefore I can only use SPI EEPROM method or ONFI. 

3. I am unclear about the ONFI. If my NAND supports this, and I use silicon 1.4 of DM355 (which supports ONFI), then how does this work?

4. The NAND I am interfacing to (MT29F8G08ABABA) is on the list of supported NAND, so I ajust wondering how it was verified.  http://processors.wiki.ti.com/index.php/List_of_NANDs_devices_supported_by_TI_RBLs#DM335.2F355

Thanks

Jamie

is it a "CE don't care" question?

I met a problem "K9F1G08U0B cannot work with DM365", did you get the same problem?

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/t/108827.aspx

I am not actually the code so i am not seeing the errors first hand.

AS I mentioned there is a lot of information on this topic so I will post results once we have it working. I have just found out that we are actually using silicon version 1.1 of the DM355 so the ONFI and SPI boot method will not work.

I see that there has been success with interfacing to NAND that has a multiple.

http://processors.wiki.ti.com/index.php/Davinci/Sitara/Integra_Nand_Boot_FAQ#The_NAND_block_size_is_a_multiple_of_what_the_RBL_interprets._Can_I_still_boot_through_this_NAND.3F

We will try this method.

Thanks

I have a customer using TMS320DM355 (silicon rev1.1) and they are migrating to Micron MT29F8G08ABABAWP.

They have tried the method to read 4^th byte and use “multiples” as explained in this post:

http://processors.wiki.ti.com/index.php/Davinci/Sitara/Integra_Nand_Boot_FAQ#The_NAND_block_size_is_a_multiple_of_what_the_RBL_interprets._Can_I_still_boot_through_this_NAND.3F

But their response is:

“Once the RBL (in silicon rev 1.1) set the default values for its module (in our case, even with old flash), we cannot change it, and using default values for new flash could boot the system with first part of boot loader (in block 0), but cannot continue to work. To verify my results I am going to test the new revision of silicon which at least for Micron read wrong block but based on the link that you sent, it should work (because its multiple).”

I have explained that rev1.4 silicon has several methods to read the NAND parameters (ONFI or EEPROM method) and they are waiting on samples now to test them.

The questions I am trying to get answers for are:

1.       Will the rev1.1 version of silicon be phased out?

2.       When is the last time buy?

3.       Is version 1.4 shipping now?

4.       What does RBL set in EMIF module when it finds the NAND parameters?

Also, if they use the EEPROM method to set NAND values, how do we find the "Block shift (Number of bits by which block address is to be shifted)" ?

Thanks

To find the "Block shift value" I found the following information from Micron.

"The device has 4096 + 224 bytes/page, 128 pages per Block.  This is also a dual plane device.

If you check table 1 on page 16 of the data sheet, you see that the block addressing starts in the 4^th address cycle and continues on the 5^th address cycle.  You will need to check with TI how they want the block shift set for that configuration."

Is there a document that can help explain how this is calculated or set?

Jamie

Jamie,

I hope to get back with you soon with answer to your question.

Marcus