[FAQ] TDA4VM: Query regarding CPSW9 MAC port mapping with PHYs

Vishal, 

Each of the 8 CPSW MACs can be configured as RGMII, SGMII, or QSGMII ports. For RGMII and SGMII, the port number is labeled as Port 1, 2, ....8. So RGMII are only limited by pinmux, and SGMII only limited by SERDES mux schemes. 

A word of warning about indexing - Note that Port 0 generally refers to the host port. BUT, in the TRM, for registers addresses indexed for ports, j=0 refers to Port 1. 

For QSGMII, four Gbe shares a common 5Gbps SERDES lane. There are two QSGMII interfaces based on SERDES muxing, so you can assign ports as following:

• The CPSW only specifies that the first three QSGMII_SUBs will go to QSGMII[0], and the second three QSGMII_SUBs will go to QSGMII[1]
• There is no requirement for the QSGMII port itself, only which ones are sent to the first QSGMII!
• The only requirement is the QSGMII lane chosen, also ties that CPSW SGMII port to the QSGMII Phy port 0

For example, on the EVM, we have QSGMII connection to the quad-ethernet daughter card, and SERDES0 Lane  1 is configured as QSGMII per SERDES mux, that is connected to the Port 2 of CPSW. So we set CPSW Port 2 as the primary QSGMII ports, mapping to Port 0 on the external QSGMII PHY. The other three ports, Port 1, 3, 4, are set as QSGMII sub mode, as shown below:

 Detailed integration view are as follows, this information is not in the TRM.  

regards

jian