AM6412: PRU-ICSS EtherCAT Slave Controller Register

Hi

0-7 bit tracks Invalid frame counter, not RX Error counter. Can you clarify whether the question is regarding Invalid frame counter or RX Error counter?

Reference for register description : https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/ETHERCAT_SLAVE_CONTROLLER_REGISTER_LIST.html

If you are talking about bit 0-7, I did some testing with TwinCAT and following are the observations.

• Testing with slave in INIT state : The counter does not reset on link break.
• Testing with slave in OP state : The counter does reset. But a potential reason for this is that TwinCAT master writes to these counters and as mentioned in the register description for 0x300, these registers are cleared if any of the counters (0x300-0x30b) is written.

Regards
Dhaval Khandla

Hi Dhaval,

Thank you for your reply. Sorry, I'm a little confused regarding how to read the table below.

Does the table section not refer to bits 0-7 of the RX Error counter?

Also, yes they are asking about 0-7 bits. Thank you for testing the connections. I will let my customer know.

Best regards,

Mari

Hi
Actually the register name is "RX Error Counter", but bit 0-7 is Invalid frame counter and bit 8-15 is Rx Error counter. Hence I wanted to confirm whether you were asking about bit 0-7 or bit 8-15.



Regards
Dhaval Khandla

Hi Dhaval,

Thank you for clearing up my misconception! I will mark this thread as resolved once I reply to my customer.

Best regards,

Mari Tsunoda