Hi Team,
The customer observed a strange behavior during AM5716 IC2 master send slave address. I2C5 master couldn't get bus busy for Transfer and send data at ack bit timing as below. It's happened 1 time / 2 to 3 hours.
I2C5 communicate with externa RTC. I2C5 module stay at Line15 which bus busy in the attached code.
Do you have any idea for this issue?
/* Set i2c slave address */
I2CMasterSlaveAddrSet( baseAddress, slaveAddress );
I2CFIFOClear(baseAddress, I2C_TX_MODE);
I2CFIFOClear(baseAddress, I2C_RX_MODE);
/*Clear all interrupt status*/
I2CMasterIntClearEx(baseAddress, I2C_INT_ALL);
/* Set data count */
I2CSetDataCount( baseAddress, size+1 );
/* Configure i2c as master-transmitter and to generate stop condition */
I2CMasterControl(baseAddress, I2C_CFG_MST_TX);
/* generate start */
I2CMasterStart(baseAddress);
/* wait for bus busy */
while(I2CMasterBusBusy(hwAttrs->baseAddr)==0)
{
}
// data TX
for (i = 0; i < (size+1); i++){
/*Wait for transmit interrupt to occur*/
while (I2CMasterIntRawStatusEx(baseAddress,
I2C_INT_TRANSMIT_READY) != I2C_INT_TRANSMIT_READY) {
｝
/* Send the data */
I2CMasterDataPut(baseAddress, txBuf[i] );
/*Disable transmit ready and stop condition interrupt*/
I2CMasterIntClearEx(baseAddress, I2C_INT_TRANSMIT_READY);
}
/* generate stop when requested */
I2CMasterStop(baseAddress);
/*Clear data buffer length*/
I2CSetDataCount(baseAddress, 0);
Thanks and Best regards,
Kuerbis
