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DM368 IPIPE clockdivider ?

star zhou
Intellectual 390 points

 
  Hi, Ti,

        We use dvsdk_2_10_01_18 for 5M jpeg encode on DM368,  and write ipipe_clkdiv to for 96MHz.
 utemp = 0x2fa9; /* 48/170*340 = 96Mhz */
 regw_if(utemp, IPIPEIF_CLKDIV);
 We found the program will hang at do_preview_resizer()  every 10minuters ~ 60minutes;
   
     But we change ipipe_clkdiv to 80MHz, the program will run better, but we need the program run
a week.
  
    Can you give me some suggestion how to avoid the program hang, and give me a suitable ipipe_clkdiv ?

     Give me some suggestion or solution for  the program avoiding at do_preview_resizer().

    Thank you !

    Zhou

  • 0
    TI__Mastermind 19985 points

    Hi,

    As you noticed, bringing down the clock of the IPIPE to 80MHz made it work reliably. The "hang" that you reported on the 96MHz setting is caused because IPIPE/RSZ is not able to write out the data to DDR with in specified time controlled by the input clock. This means that due to DDR bandwidth load, you need to slow down the processing and output generation of IPIPE.

    So 80MHz is possibly good enough for your system load.

    BTW, what is your data flow in the system? Are you using continuous mode of operation? I guess no, because you can see that clock divider is making change to IPIPE/RSZ operation. What is the resolution of capture data from ISIF and the resolution of data that is generated from RSZ.

    I would recommend you to use continuous mode of operation, if you dont need resizers to be used separately. This will take away any dependency on the IPIPE clock and also reduce DDR bandwidth considerably.

    Regards,

    Anshuman

    PS: Please mark this post as verified, if you think it has answered your question. Thanks.