TMDS243GPEVM: AM243x: Sync start multiple EPWMs

Johannes von Löwis

Part Number: TMDS243GPEVM

Hello,

I have managed to sync start EPWMs 0 to 3 by clearing and setting bits in register CTRLMMR_EPWM_TB_CLKEN.

First I tried to use registers CTRLMMR_EPWM_TB_CLKEN_SET and CTRLMMR_EPWM_TB_CLKEN_CLR which, according to TRM sections 5.1.1.5.46 and .47, should set and clear bits in CTRLMMR_EPWM_TB_CLKEN but this did not work. I had to write 0x0 directly to CTRLMMR_EPWM_TB_CLKEN to stop EPWMs 0 to 3 and write 0xf to start EPWMs 0 to 3. (Before accessing those registers I disabled write protection using CTRLMMR_LOCK1_KICK0 and CTRLMMR_LOCK1_KICK1.)

Now my questions:

What is the purpose of registers CTRLMMR_EPWM_TB_CLKEN_SET and CTRLMMR_EPWM_TB_CLKEN_CLR? What is the correct way of using them?

What is the preferred way of accessing memory mapped registers like CTRLMMR_EPWM_TB_CLKEN? I did the following:

*CTRLMMR_EPWM_TB_CLKEN_CLR = 0xf; // disable clocks to EPWM0,...,EPWM3 ... doesn't work
*CTRLMMR_EPWM_TB_CLKEN = 0; // disable clocks to EPWM0,...,EPWM3

// init EPWMs ...

*CTRLMMR_EPWM_TB_CLKEN_SET = 0xf; // enable clocks to EPWM0,...,EPWM3 ... doesn't work
*CTRLMMR_EPWM_TB_CLKEN = 0xf; // enable clocks to EPWM0,...,EPWM3

with the following #defines

#define CTRLMMR_EPWM_TB_CLKEN ((volatile uint32_t *) 0x43004130)
#define CTRLMMR_EPWM_TB_CLKEN_SET ((volatile uint32_t *) 0x43004134)
#define CTRLMMR_EPWM_TB_CLKEN_CLR ((volatile uint32_t *) 0x43004138)

I would have expected at least such #defines (or something similar) to be provided by TI but I could not find a file containing such definitions. Where should I look?

Best regards,

Johannes

over 3 years ago

+1 Frank Livingston over 3 years ago

TI__Mastermind 29348 points

Hi Johannes,

Johannes von Löwis said:
First I tried to use registers CTRLMMR_EPWM_TB_CLKEN_SET and CTRLMMR_EPWM_TB_CLKEN_CLR which, according to TRM sections 5.1.1.5.46 and .47, should set and clear bits in CTRLMMR_EPWM_TB_CLKEN but this did not work. I had to write 0x0 directly to CTRLMMR_EPWM_TB_CLKEN to stop EPWMs 0 to 3 and write 0xf to start EPWMs 0 to 3.

Johannes von Löwis said:
What is the purpose of registers CTRLMMR_EPWM_TB_CLKEN_SET and CTRLMMR_EPWM_TB_CLKEN_CLR

This is a hardware bug, please see this previous e2e thread on this topic: https://e2e.ti.com/support/processors/f/processors-forum/993871/am6442-epwm-tb_clken

Johannes von Löwis said:
What is the preferred way of accessing memory mapped registers like CTRLMMR_EPWM_TB_CLKEN?

Please see <SDK>\source\drivers\soc\am64x_am243x\soc.c:SOC_setEpwmTbClk(). This function uses R-M-W to set a single bit in CSL_MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN.

You can use this code as an example of how to write CTRLMMR_EPWM_TB_CLKEN, i.e. use the following:

CSL_REG32_WR()
CSL_CTRL_MMR0_CFG0_BASE
CSL_MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN

These definitions are provided in files in the these folders:

<SDK>/source/drivers/hw_include/
<SDK>/source/drivers/hw_include/am64x_am243x/

Regards,
Frank

0 Johannes von Löwis over 3 years ago in reply to Frank Livingston

Expert 1806 points

Hi Frank,

thank you for pointing me to soc.c.

SOC_setEpwmTbClk() uses SOC_controlModuleUnlockMMR() and SOC_controlModuleLockMMR().

The call of SOC_controlModuleLockMMR() leaves the MMR registers unlocked, since the locking code is commented out by #if 0 (for MAIN domain).

Best regards,

Johannes

+1 Frank Livingston over 3 years ago in reply to Johannes von Löwis

TI__Mastermind 29348 points

Hi Johannes,

Thanks for pointing this out. I see this in the code:

#if 0 /* in AM64x, main dowmin MMRs are left unlocked since when working with linux kernel, linux kernel assumes MMRs are unlocked */

This seems like an oversight to me, since AM243x won't run Linux. I'll raise this issue with the software development team.

In the meantime, you should be able to add the MMR locking back into the code and rebuild the drivers library.

Regards,
Frank

Processors

Processors forum

TMDS243GPEVM: AM243x: Sync start multiple EPWMs