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AM6412: DDR4-SDRAM layout

Part Number: AM6412

Hi team,

 

I’ve got question regarding on AM6412 DDR4-SDRAM layout. Could you please take a look below?

On the Layout Guidelines (here) figure 2-4, SDRAN Byte 0 is shown upper side, and Byte 1 is shown bottom side.

Table 2-5 indicates that BYTE0=DQS0,DQ[7:0] and BYTE1=DQS1,DQ[15:8].

Figure 2-7 also indicates connection from processor to the BYTE0 device.

However, AM6412 has pin configuration which has A1 closed to DQ[7:0] group, and L/M/N closed to DQ[15:8] group. So if I follow the guideline the DQ lines would be crossed.

 

Right now I’m struggling to understand how the guideline can be followed without crossed lines. Would you please advise? Also, if there is misunderstanding, please let me know.

Best regards,

Kurumi

  • Kurumi, you are correct.  Byte 0 should be below Byte 1 in the diagram for optimal routing.  I think the byte designation on the DDR blocks was intended to be more ambiguous.  However, we will correct this in the next version of the app note to avoid confusion. 

    Regards,

    James

  • Hi James, 

    Thank you for the reply. I understand the Byte 0 should be below Byte 1 on Figure 2-4.

    So when connecting CK/ADDR_CTRL group using Flyby topology, is the routing shown below picture  {BYTE1(DQ15:8)→BYTE0(DQ7:0)→Termination resistor} correct?

    I'm assuming Figure 2-7 is from top view.

    Best regards,

    Kurumi

  • Kurumi, i think the Byte0/1 designation in the diagrams is meant to be ambiguous.  It doesn't matter the order of each byte along the fly-by, as long as you keep the data signals in each byte lane together (ie, DQ[7:0[ with DQS0 and DM0, and DQ[15:8] with DQS1 and DM1) 

    So you could route CK/ADDR/CMD as {BYTE1(DQ15:8)→BYTE0(DQ7:0)→Termination resistor}  or {BYTE0(DQ7:0)→BYTE1(DQ15:8)→Termination resistor.  It just depends on which is easier to route on your board.

    Regards,

    James

  • Hi James,

    Understood, thank you so much for your help.

    Best regards,

    Kurumi