TDA4VM: If both PCIE and TIDL processes are enabled at the same time, they will hang up.

add pcie demo : pcie_manager   /cfs-file/__key/communityserver-discussions-components-files/791/demo_2D00_pcie_5F00_manager.zip

From QNX: The pcie_manager uses the udma controller to transfer the stream data. What about TIDL ?

@TI engineers, Could you help to confirm this information, thanks.

HI, Chao, 

Can you pls help to share your  logs ? Is there any error ? My suggestions as below : 

1. When TIDL is started first and then pcie manager is started, TIDL exits abnormally

    Can you pls help to explain the abnormal ? 

Can you pls using CCS to connect C7x and check the status? Thanks. 

Regards, 

Fredy Zhang 

Hi，Fredy

I have a problem with the CCS environment and can't use it ，Can it be verified by adding log information?

Hi，Fredy

I have a problem with the CCS environment and can't use it ，Can it be verified by adding log information?

Phenomenon：I enable TIDL first and then enable PCIE, the TIDL process will be killed and  the terminal does not output relevant information.

Hi, Chao, 

Can you pls set several breakpoint at the PCIE initialization ？ Then you can check which resource is conflicts with TIDL. 

Can you pls share your log ? is there any error ? 

Regards, 

Fredy Zhang 

Hi Fredy,

What is the memory range used by TIDL?

From QNX:

When the PCIe used "/memory/ram/sysram"(over 4G) region, the problem occurs.

I checked the system_memory_map.html but can't find the overlapped region with "/memory/ram/sysram"(0000000880000000-00000008fcfdefff).

Hi Chao,

Regarding the theory that this could be a possible memory conflict between Vision Apps and PCIe, recommend looking at the memory layout in use in the system:

1) Vision Apps / TIDL

Vision Apps requires a range of DDR memory be reserved for its use.   This memory is not to be used by applications outside of the vision apps framework.   For example a malloc() from the QNX HLOS should never use memory in this reserved range.   Similarly an application such as PCIE should not be mapping anything into this memory region, which is reserved for the vision app framework.   

The vision apps memory requirements are captured in the ./vision_apps/apps/basic_demos/app_tirtos/tirtos_qnx/system_memory_map.html, of the release PSDK RTOS Release that is being used. 

If any memory layout changes are made to the Vision Apps framework, the PSDK QNX memory must similarly be updated, see (2)

2) QNX HLOS / PSDK QNX

To ensure the QNX HLOS does access the memory reserved for the Vision Apps framework, during initialization the QNX startup is informed that the memory is reserved, and the HLOS should not use it.  The TI PSDK QNX documentation covers this at below link:

9.3. How To Take Care Of Remote Core Memory Map Updates — Processor SDK QNX J721E (ti.com)

This carveout will ensure no dynamic memory allocation from the HLOS, will be done in the memory region reserved for Vision Apps framework in (1).  The carveout does not prevent a driver such as PCIe from inadvertently mapping directly to that space.

The carveout in (2) must align with ./vision_apps/apps/basic_demos/app_tirtos/tirtos_qnx/system_memory_map.html from (1)

3) PCIe

PCIe may have dedicated memory regions assigned to it, for it needs.   These memory regions and how they are being defined are not part of TI deliverables.   Please ensure that the PCIe memory in use does not conflict with the Vision Apps Framework memory layout as defined in (1).

If PCIe is only using /memory/ram/sysram, and the carveout in (2) is aligned with the system memory map in (1), then there should not be a memory conflict.

4)  If you would like, please provide the below information and TI can review for (1) and (2)

• The /vision_apps/apps/basic_demos/app_tirtos/tirtos_qnx/system_memory_map.html from the build environment under test
• The output from "pidin syspage=asinfo" as run from the QNX command prompt

If you have any additional information on the memory used by (3), that can be provided as well.

Regards,

kb

Hi KB,

1. 

• The /vision_apps/apps/basic_demos/app_tirtos/tirtos_qnx/system_memory_map.html from the build environment under test

system_memory_map.html  should be ./vision_apps/apps/basic_demos/app_rtos/rtos_qnx/system_memory_map.html in SDK8.0.

/cfs-file/__key/communityserver-discussions-components-files/791/0184.system_5F00_memory_5F00_map.html

• The output from "pidin syspage=asinfo" as run from the QNX command prompt

J7EVM@QNX:/# pidin syspage=asinfo
Header size=0x00000108, Total Size=0x00000dd8, #Cpu=2, Type=257
Section:asinfo offset:0x000005f8 size:0x000002a0 elsize:0x00000020
0000) 0000000000000000-0000ffffffffffff o:ffff a:0010 p:100 c:0 n:/memory
0020) 0000000000000000-00000000ffffffff o:0000 a:0010 p:100 c:0 n:/memory/below4G
0040) 0000000080000000-00000000ffffffff o:0020 a:0017 p:100 c:0 n:/memory/below4G/ram
0060) 0000000880000000-00000008ffffffff o:0000 a:0017 p:100 c:0 n:/memory/ram
0080) 0000000001800000-000000000180ffff o:0000 a:0003 p:100 c:0 n:/memory/gicd
00a0) 0000000001900000-000000000193ffff o:0000 a:0003 p:100 c:0 n:/memory/gicr
00c0) 000000008001d800-000000008001dfff o:0000 a:0007 p:100 c:0 n:/memory/hypervisor_vector
00e0) 00000000800d10a8-00000000817c3e83 o:0000 a:0005 p:100 c:0 n:/memory/imagefs
0100) 0000000080080fa0-00000000800d10a7 o:0000 a:0007 p:100 c:0 n:/memory/startup
0120) 00000000800d10a8-00000000817c3e83 o:0000 a:0007 p:100 c:0 n:/memory/bootram
0140) 0000000000000000-00000000ffffffff o:ffff a:0010 p:100 c:0 n:/virtual
0160) ffffff8060055000-ffffff8060136540 o:0140 a:0000 p:100 c:0 n:/virtual/vboot
0180) 0000000080000000-0000000080007fff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01a0) 000000008001d000-000000008001cfff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01c0) 000000008001f000-000000008001ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01e0) 0000000080026000-000000008002ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0200) 0000000080032000-000000008003ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0220) 0000000080042000-000000008007ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0240) 00000000817c4000-00000000817cffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0260) 0000000081fd0000-000000009fffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0280) 0000000880000000-00000008fcfdefff o:0060 a:0007 p:100 c:0 n:/memory/ram/sysram

2. We did not reserved for remote core using startup-j721e-evm parameters.

3. The test result as following:

1) PCIe use /memory/ram/sysram, then PCIe and TIDL will overlap, then system crash. But we can't find overlay in system_memory_map.html and can't find TIDL in system_memory_map.html.

2) PCIe use /memory/below4G/ram/sysram instead /memory/ram/sysram, the PCIe and TIDL work normally.

Please help to find why the memory overlay orccur and please to clearly give the memory range of TIDL, Thanks.

Hi KB,

We also do a test.

First, add a new memory range.

diff --git a/boards/j721e/init_raminfo.c b/boards/j721e/init_raminfo.c
index c3849a4..e43535e 100644
--- a/boards/j721e/init_raminfo.c
+++ b/boards/j721e/init_raminfo.c
@@ -32,7 +32,13 @@ void init_raminfo()
add_ram(IDK_DDR0_BASE, IDK_DDR0_SIZE);
#endif
#ifdef IDK_DDR1_SIZE
+ kprintf("%s: add_ram for DDR1 -> base 0x%lx, size %d\n", __func__, IDK_DDR1_BASE, IDK_DDR1_SIZE);
add_ram(IDK_DDR1_BASE, IDK_DDR1_SIZE);
+
+ // this is working
+ paddr_t start = IDK_DDR1_BASE + GIG(1);
+ paddr_t end = start + GIG(1) - 1;
+ as_add_containing(start, end, AS_ATTR_RAM, "pcie", "memory");
#endif
}

And then the pidin syspage=asinfo output change to the following. When the PCIe using the /memory/ram/pcie/sysram, there will be not problem.

J7EVM@QNX:/# pidin syspage=asinfo
Header size=0x00000108, Total Size=0x00000e20, #Cpu=2, Type=257
Section:asinfo offset:0x00000600 size:0x000002e0 elsize:0x00000020
...
0280) 0000000081970000-00000000fcfdefff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
02a0) 0000000880000000-00000008bfffffff o:0060 a:0027 p:100 c:0 n:/memory/ram/sysram
02c0) 00000008c0000000-00000008ffffffff o:0080 a:0007 p:100 c:0 n:/memory/ram/pcie/sysram

Hi KB

We found that the memory used by C7X_1 was inconsistent with what was provided in the system_memory_map.html.

In the code, vision_apps/apps/basic_demos/app_rtos/rtos_qnx/c7x_1/main.c define the C7X_1 address.

"DDR_C7X_1_LOCAL_HEAP_PADDR (0x880000000u)"

In the system_memory_map.html, it is

Please help to confirm the reason for the inconsistency between the two and which one shall prevail.

Hi Chao,

Regarding the system_memory_map.html, agreed that this does not look correct, when compared to the carveout.   Note that the 0x100000000, is a virtual address that maps to 0x880000000.

The code changes for pcie only memory you have made, are reasonable, however, the C7x expected memory reservation would still be exposed to A72 applications other than PCIe.

Referencing PSDK 7.3, which uses 1 GB for C7x, The memory 0x88000000, to 0x08c000000 needs to be removed from the QNX HLOS view of available memory.

The psdkqa/qnx/bsp/images/j721e-evm-ti.build file for the IFS could be modified as below to ensure that the QNX HLOS does touch the 1G that is reserved for the C7x.

[+keeplinked] startup-j721e-evm -v -r0xA0000000,0x60000000,1 -r0x880000000,0x40000000-d

Which would give the below output from "pidin syspage=asinfo", where 0x880000000 to 0x8c0000000 is no longer available for QNX HLOS on the A72.

01a0) 0000000080000000-0000000080007fff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01c0) 0000000080010000-000000008000ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01e0) 0000000080014000-000000008007ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0200) 000000008111e000-000000009fffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0220) 00000008c0000000-00000008fcfdefff o:0060 a:0007 p:100 c:0 n:/memory/ram/sysram

Please note, have not tested this build file modification other than to generate the above "pidin syspage=asinfo" output.

Regards,

kb

Hi Chao,

Previous response was based on SDK 7.3 where C7x expected 1 GB to be reserved, I have gone back and edited to be more explicit.   

For a release like SDK 8.1 where C7x only requires 256 MB, then build file modification would be as below:

[+keeplinked] startup-j721e-evm -v -r0xA0000000,0x60000000,1 -r0x880000000,0x10000000 -d

Which would give the below output from "pidin syspage=asinfo", where 0x880000000 to 0x890000000 is no longer available for QNX HLOS on the A72.

01a0) 0000000080000000-0000000080007fff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01c0) 0000000080010000-000000008000ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
01e0) 0000000080014000-000000008007ffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0200) 000000008111e000-000000009fffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram
0220) 0000000890000000-00000008fcfdefff o:0060 a:0007 p:100 c:0 n:/memory/ram/sysram

Regards,

kb

Hi KB,

I found the DDR_C7X_1_LOCAL_HEAP in map file vx_app_rtos_qnx_c7x_1.out.map is still using the 0x100000000.

vision_apps/out/J7/C71/SYSBIOS/release/vx_app_rtos_qnx_c7x_1.out.map
DDR_C7X_1_LOCAL_HEAP  000100000000   10000000  10000000  00000000  RWIX

It seems be link by linker_mem_map.cmd.

vision_apps/apps/basic_demos/app_rtos/rtos_qnx/c7x_1/linker_mem_map.cmd
DDR_C7X_1_LOCAL_HEAP     ( RWIX ) : ORIGIN = 0x100000000 , LENGTH = 0x10000000

Should I also change the  linker_mem_map.cmd to 0x880000000 as following ?

DDR_C7X_1_LOCAL_HEAP     ( RWIX ) : ORIGIN = 0x880000000 , LENGTH = 0x10000000

Hi Chao,

The C7x related variables do not need to be modified, please refer to the comments in the file below:

ti-processor-sdk-rtos-j721e-evm-08_01_00_11/vision_apps/platform/j721e/rtos/c7x_1/main.c

/* For J7ES/J721E/TDA4VM the upper 2GB DDR starts from 0x0008_8000_0000 */
/* This address is mapped to a virtual address of 0x0001_0000_0000 */
#define DDR_C7X_1_LOCAL_HEAP_VADDR (DDR_C7X_1_LOCAL_HEAP_ADDR)
#define DDR_C7X_1_LOCAL_HEAP_PADDR (0x880000000u)

The only modification required for PSDK QNX release 8.1, is that the BSP build file must be set to ensure memory range 0x8_8000_0000 to 0x8_9000_0000 is not used by the QNX HLOS.  This can be done by making the below change and rebuilding the QNX-IFS.

[+keeplinked] startup-j721e-evm -v -r0xA0000000,0x60000000,1 -r0x880000000,0x10000000 -d

Regards,

kb

Hi KB,

When we reserved the memory range 0x880000000 to 0x890000000, the TIDL will has some problem. So It seems the TIDL has some program run on A72.

We just solved this by simply not using physical addresses 0x880000000 to 0x890000000.

Thanks.