AM3358: Command to SD-card fails with timeout

May be I should add some information about where this timeout occurs (may be it happens with all types of commands/data transfers, but this is where I see it first):

Command type is MMCHS_CMD_CMD_TYPE_NORMAL

Command direction is read (MMCHS_CMD_DDIR_READ)

Command is 17

Response type is MMCHS_CMD_RSP_TYPE_48BITS

And even when I do not rely on the ISR but poll the CTO and CC bits of the STAT register (but still with EDMA enabled), the result is the same, so it has nothing to do with the bits arriving too late/never when the ISR is used.

Some more findings about this issue: It seems it has nothing to do with IRQ/EDMA handling of the SD-card. When I implement the SD-card-functions in the main application in the same way like it is done in bootloader (means using the polling-way), the problem still exists. So the reason must be some other, general difference between bootloader code and "normal" code.

On the thing that comes into my mind is the whole chaching / MMU stuff which is enabled at the very beginning of the application but which is not active for the bootloader:

void MMUConfigAndEnable(void)
{
    /*
    ** Define DDR memory region of AM335x. DDR can be configured as Normal
    ** memory with R/W access in user/privileged modes. The cache attributes
    ** specified here are,
    ** Inner - Write through, No Write Allocate
    ** Outer - Write Back, Write Allocate
    */
    REGION regionDdr = {
                        MMU_PGTYPE_SECTION, START_ADDR_DDR, NUM_SECTIONS_DDR,
                        MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
                                                         MMU_CACHE_WB_WA),
                        MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                        (unsigned int*)pageTable
                       };
    /*
    ** Define OCMC RAM region of AM335x. Same Attributes of DDR region given.
    */
    REGION regionOcmc = {
                         MMU_PGTYPE_SECTION, START_ADDR_OCMC, NUM_SECTIONS_OCMC,
                         MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA,
                                                          MMU_CACHE_WB_WA),
                         MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
                         (unsigned int*)pageTable
                        };

    /*
    ** Define Device Memory Region. The region between OCMC and DDR is
    ** configured as device memory, with R/W access in user/privileged modes.
    ** Also, the region is marked 'Execute Never'.
    */
    REGION regionDev = {
                        MMU_PGTYPE_SECTION, START_ADDR_DEV, NUM_SECTIONS_DEV,
                        MMU_MEMTYPE_DEVICE_SHAREABLE,
                        MMU_REGION_NON_SECURE,
                        MMU_AP_PRV_RW_USR_RW  | MMU_SECTION_EXEC_NEVER,
                        (unsigned int*)pageTable
                       };

    /* Initialize the page table and MMU */
    MMUInit((unsigned int*)pageTable);

    /* Map the defined regions */
    MMUMemRegionMap(&regionDdr);
    MMUMemRegionMap(&regionOcmc);
    MMUMemRegionMap(&regionDev);

    /* Now Safe to enable MMU */
    MMUEnable((unsigned int*)pageTable);
}

void CacheEnable(unsigned int enFlag)
{
    if(enFlag & CACHE_ICACHE)
    { 
        CP15ICacheFlush();
        CP15ICacheEnable();
    }

    if(enFlag & CACHE_DCACHE)
    {   
        /* For Cortex A8, L2EN has to be enabled for L2 Cache */
        if(PRIMARY_PART_CORTEX_A8 == CP15MainIdPrimPartNumGet())
        {
            CP15AuxControlFeatureEnable(CORTEX_A8_L2EN);
        }

        CP15DCacheFlush();
        CP15DCacheEnable();
    }
}

The problem: I definitely can't disable this globally, the whole application would become way too slow without them.

Hello,

Please refer to this thread which discussed about a similar issue to yours. Please also note that TI has stopped supporting TI-RTOS and bare-metal SW development for AM335x devices, as announced here. Please take a look at the announcement and find collateral resources there. We will not be able to provide continuing responses for this inquiry.

Thank you for your understanding.

Regards,

Jianzhong

Sorry but the thread you are referring to has absolutely nothing to do with my problem.

There: the APP bootloader is not loaded by the processor.

Here: the APP bootloader loads perfectly, the code within the APP bootloader can access the SD card perfectly but the (last stage) application that is finally running with MMU enabled fails accessing some specific SD-cards.

The timeout I'm talking about is a timeout announced by the CTO flag in STAT register while accessing the SD.card hardware out of the application.