J721EXSOMXEVM: CPSW Driver on A72 Questions

Daniel Merrill

Prodigy 30 points

Part Number: J721EXSOMXEVM

I’m using the u-boot cpsw driver as an example, but note that its using the MCU-CPSW0, which if I understand the documentation correctly is accessed by the r5 registers. The driver is running on A72 cores and from what I see/understand this doesn’t have access to the MCU-CPSW. Is that correct?
If #1 is correct, I believe I need to access the other CPSW mapped at 0xC0000000 is that understanding correct?
In trying to do #2 I’m attempting to set up the DMA queues via tisci, but running into an issue when trying to do a PSIL pair command. I’m attempting to pair source thread ID 0x1000 to dest thread ID 0xCA00 as I believe those are the values I’m looking for based on https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/psil_cfg.html#psi-l-proxy-device-ids. However while I do get a response it’s not acked, but I’ve been unable to identify why that would be the case. Any help you can provide on this front would be great.

over 3 years ago

0 Stanley Liu over 3 years ago

TI__Guru 50045 points

1. u-boot ethernet driver is for MCU_CPSW0 (a.k.a. CPSW2G). It is controlled from A72 directly, not R5.

This is the same interface supported by Linux CPSW2G driver on A72.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/08_01_00_07/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW2g.html

2. The CPSW base address at 0x0C00_0000 is Main domain CPSW0 (a.k.a. CPSW9G).

You can refer to the below link for more details.

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_01_00_13/exports/docs/psdk_rtos/docs/user_guide/developer_notes_ethfw.html

3. I am not clear what you are trying to here in relationship to #2 since CPSW9G is in main domain.

Please refer to the above link to find out more about how EthFW works.

0 Daniel Merrill over 3 years ago in reply to Stanley Liu

Prodigy 30 points

Currently I’m suspecting right now since this seems to be where I get stuck is that my ring accelerators aren’t configured correctly. I think I’m currently configuring them the same as what u-boot does/did, however one interesting thing to note and I don’t know if this is normal or not, but it seems abnormal to me is that when I perform a TISCI_MSG_RM_RING_CFG I don’t see any of the values reflected in the corresponding ring cfg registers. I would have expected that I would be able to validate via the Lauterbach that they got set correctly, but I just continue to see 0’s. Is that normal behavior? Attached are the parameters I’m sending in the message if that helps.

0 Daniel Merrill over 3 years ago

Prodigy 30 points

I'm still having trouble writing to certain registers. i.e. thchanrt registers for the udma. I have them mapped and the write appears to work, but there is no side affect of the write. Any idea what might be the cause here?

0 Daniel Merrill over 3 years ago in reply to Daniel Merrill

Prodigy 30 points

The issue appears to be that these registers are only accessible in privileged mode. I could not find this documented but this appears to resolve this issue.

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J721EXSOMXEVM: CPSW Driver on A72 Questions