Part Number: AM5708
Hello all,
I'm working on a custom board which is based on AM5708 booting on a NAND.
Previously I was working with processor-sdk 06_03_00_106 which is providing linux-ti-stagging 4.19 kernel, system working fine with device tree, kernel and rootfs on the NAND.
Now I have checkout the processor-sdk 08_00_00_21 which is providing linux-ti-stagging 5.10 kernel, and basically rebuild all my yocto project with this release (of course come minor upgrade of my layer were required to use it, but no significant topics). Particularly, I have no specific kernel configuration (I'm using the default one from TI) and I have not changed my device tree at all, it's very basic.
Building provided the new kernel + devicetree + rootfs that I have flashed on the NAND.
=> Following this, I reboot the system, but it is stuck at "Starting kernel..." log. Nothing append after that :-(
I have checked the dtsi included by my device tree but don't found something relevant. I have also compared the kernel configuration, there are differences of courses, but again nothing that really seems to be interesting (at least for me). I have attached kernel configuration 4.19 and 5.10 + device tree to this post.
Note: I have kept the same u-boot version (based on 2021.01) and u-boot configuration when migrating from 4.19 to 5.10 (there is a custom board definition inside, I'm not really interested to upgrade this). basically this is loading the kernel+devicetree from the NAND and booting.
Thanks for all ideas and feedbacks that may help !
Joel
config_4.19.txtconfig_5.10.txt
/dts-v1/;
#include "dra72x.dtsi"
#include "am57xx-commercial-grade.dtsi"
#include "dra7-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "myself,my-product","ti,am5708", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
aliases {
rtc0 = &rtc;
};
chosen {
stdout-path = &uart1;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x20000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dsp1_memory_region: dsp1-memory@9c000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9c000000 0x0 0x1000000>;
reusable;
status = "okay";
};
ipu1_memory_region: ipu1-memory@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "okay";
};
ipu2_memory_region: ipu2-memory@9f000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9f000000 0x0 0x800000>;
reusable;
status = "okay";
};
};
};
&dra7_pmx_core {
nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
>;
};
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot";
reg = <0x00080000 0x00100000>;
};
partition@5 {
label = "NAND.u-boot-spl-os";
reg = <0x00180000 0x00040000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x1F600000>;
};
};
};
&rtc {
status = "disabled";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
};
&uart1 {
status = "okay";
};
&dsp1 {
status = "okay";
memory-region = <&dsp1_memory_region>;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_memory_region>;
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_memory_region>;
};
