AM6526: Input Slew Rate Clarification

Hi Shiou,

Thanks for the support so far. The customer is wondering if there are any other reasons as to why the slew rate is slower despite the clock frequency being faster? Also, if the slew rate is assessed at a smaller time frame, wouldn't the slew rate not change because it is a slope?

Best regards,

Mari Tsunoda

Hi Shiou,

Sorry for the follow-up question once again.

I understand that the min slew rate value indicates that higher speed modes have higher slews.

Why, at the max value, would the slope be smaller for the higher speed mode? Shouldn't it also be greater?

Best regards,

Mari

Hi Shiou,

Thank you for explaining the calculations. I believe you meant Legacy SDR yields 2.64 V/ns whereas High Speed SDR yield 2.06V/ns. I understand that minimum slew is 1ns vs. maximum slew differs for the two modes. Could you point me to where on the JEDEC specification document it says this? Just want to be able to refer it for the customer.

Best regards,

Mari

Hi Shiou Mei,

Thank you for supporting this thread. Just easy question, Where is the description which you mentioned below in the JEDEC specification document ? 

The slew rate came directly from the JEDEC specification, the Legacy SDR timing slew was assessed at 10%-90% while the high Speed SDR was assessed at 12.5%-75%,

Thanks and regards,
Hideaki

Hi Shiou,

I am jumping in...Table A.222 and Table 208 are from the most recent "v5.1A" spec - the AM6526 DS/TRM state the "v4.5" spec as their reference spec.
In the v4.5 spec, I believe the proper tables you are indicating are as below:

① Table A.222(v5.1A) --> Table 166(V4.5)
② Table 208(v5.1A) --> Table 157(v4.5)

For ① above, both specs do have a comment in the NOTES section that Tr/Tf are, quote:

NOTE 2 Rise and fall times are measured from 10%-90% of voltage level.

But for ② above, neither v5.1A or v4.5 specs mention Tr/Tf as 12.5%~75% ...
Instead, they state:

NOTE 4. CLK rise and fall times are measured by min (VIH) and max (VIL).

The tables we need to find min(VIH) and max(VIL) are Table 151~154; and the threshold varies based on VCCQ.
Could you please confirm what voltage VCCQ was when we did characterization and wrote the AM65xx Datasheet?

Assuming VCCQ = 3.3V, then from Table 152 (v4.5) we see:

VOL "max" = 0.125*VCCQ = 12.5%
VOH "min" = 0.75*VCCQ = 75%

VIL "max" = 0.25 * VDD = 25%
VIH "min" = 0.625 * VCCQ = 62.5%

From the above, we see 12.5%~75% from OUTPUT voltage thresholds, not INPUT thresholds.
But from NOTE 4 as written above, we are told to consider INPUT thresholds.

Did we use VOL and VOH values for calculation, because these are the max/min thresholds the "Host" would be outputting, and the "Device" would be receiving...?
I don't quite understand the distinction...wouldn't it be 25%~62.5%? Not 12.5%~75%?

This is further confusing, as Table 7-51. MMC Timing Conditions in the DS calls this the "Input Slew Rate" the AM65xx can accept...

Regards,
Darren

Hi Shiou,

Thanks!

Just a quick follow-up to solidify my understanding...

The "Input Slew Rate" discussed in Table 7-51. MMC Timing Conditions is talking about the SD/eMMC CLK (OUT from AM65xx) signal only, right?
Also, the "Input Slew Rate" is a requirement the AM65xx has to meet as it outputs the CLK signal, to the SD/eMMC device, right?
So designers will need to be careful about bus impedance / parasitic capacitance pushing the CLK edges too fast/slow, right?

Hi Shiou,

Thank you for the clarifications and the table numbers. The customer has a few more follow-up questions. You mentioned that 1ns is the minimum slew used to calculate the maximum slew rate. I was not able to find the minimum slew value on the table for Forward-compatible host interface timing. Where did this minimum value come from? I believe they are asking this because the table 166 (v4.5) indicates has no minimum clock rise time and clock fall time value. However, the maximum slew rate was calculated with the minimum slew of 1ns. If you could give some additional insight on this, I would appreciate it.

Best regards,

Mari

Mari,

Customer's observation is correct.  Given a minimum rise/fall time was not published in the specification, we had an internal discussion to decide on a value to use for the slew rate calculation, and 1 ns was the value we determined.

Best Regards,

Shiou Mei

Hi Shiou,

I see, the customer is saying that the damping resistor they need to achieve the maximum input slew rate for the high speed SDR is too big, and therefore they are having issues.

They've posed a few more follow-up questions. 

1) If they were to go above the maximum input slew rate, what would happen?

2) Are you able to provide any insights as to what were some of the deciding factors for the 1ns during the internal discussion?

Best regards,

Mari

Mari,

What are the input slew rate customer is seeing for 3.3 V?  What is the actual slew they measured?

Thanks & Regards,

Shiou Mei

Hi Shiou,

For 3.3V Legacy SDR, with a damping resistance of 22Ω they measured 2.5V/ns. For 3.3V High Speed SDR, they said they needed a 43Ω damping resistance to achieve 2.06V/ns. 

Also, they have a question as to why they need to change the input device (with the damping resistance changes) for the two different modes. Can you provide any insight on this?

Hope this helps.

Best regards,

Mari Tsunoda

Hi Shiou,

Can I get an update on this soon?

Best regards,

Mari Tsunoda

Hi Shiou,

Could you give me an update on this?

Would like to reply soon to the customer.

Best regards,

Mari

Mari,

Note the input of our device is the output of eMMC device.  Legacy SDR mode is used to support some of the legacy devices, so timing may be different from High Speed SDR, which is a newer speed mode.  If customer plans to support both speed modes, then the more stringent & faster requirement (High Speed SDR) can be used for both scenarios and they can avoid changing the setup.

That said, I have not seen a lot of customers using damping devices on the MMC signal lanes.  Without the damping resistor, what slew/ slew rate does customer see?

Best Regards,

Shiou Mei

Hi Shiou,

Thanks for your reply. Their slew rate with no damping resistor is 3.0V/ns. 

Shiou Mei Huang said:

If customer plans to support both speed modes, then the more stringent & faster requirement (High Speed SDR) can be used for both scenarios and they can avoid changing the setup.

I see. I will let them know to use the faster requirement as you said.

Also, can you give any insight on these questions?

Mari Tsunoda said:

1) If they were to go above the maximum input slew rate, what would happen?

2) Are you able to provide any insights as to what were some of the deciding factors for the 1ns during the internal discussion?

Thank you always for your support.

Best regards,

Mari

Hi Shiou Mei,

Any update on this?

Best regards,

Mari 

Mari,

1) The slew rates were specified since they affect setup and hold time. A value above our max slew rate will eat away the hold timing margin. Since Legacy SDR is running at a slow frequency and launching on falling edge and capturing on rising edge, there are usually plenty of margin for hold.  Customer can characterize the timing on their end to determine if there are sufficient hold time despite the slew rate difference.

Aside for hold timing, you will also want to make sure the signal is not hanging near Vil and Vih.

2) Same reasoning as above. 

As for damping resistors, if it improves customer system's signal integrity, then it could make sense for customer to use them in the system.  

Best Regards,

Shiou Mei

Hi Shiou Mei,

Thanks for the support. Will let my customer know.

Best regards,

Mari