McASP Receive Bit Clock Set up

Sarah Zhang

Other Parts Discussed in Thread: OMAP-L138

Hi All,

On the OMAP_L138 EVM, I want to use McASP0 in receive mode (using 2-slot TDM I2S mode) . Master Clock (AHCLKR) is generated externally while Bit Clock (ACLKR) and frame sync (AFSR) are generated internally. I did the following McASP set up in order to achieve this

Mcasp_HwSetupData mcaspRcvSetup =
{
    /* .rmask    = */ 0xFFFFFFFF, /* all Data bits are used              */
    /* .rfmt     = */ 0x00018070, /* Receive Bit Stream Format Register
                                     * (31-18 Bits) Reserved
                                     * (17-16) RDATDLY - 1 bit delay (for I2S format),
                                     * (15)    RRCRS   - MSB first,
                                     * (14-13) RPAD    - No pad value for extra bits in slot
                                     * (12-8) RPBIT   - ignored (only used when RPAD not 0)
                                     * (7-4)   RSSZ    - 16 bits slot size
                                     * (3)     RBUSEL - Reads from XRBUF on DMA port.
                                     * (2-0)   RROT    - No rotation */
    /* .afsrctl = */ 0x00000113, /* Receive Frame Sync Control Register
                                     * (31-16) Reserved
                                     * (15-7) RMOD    - I2S mode (2-slot TDM)
                                     * (6-5)   Reserved
                                     * (4)     FRWID    - Single word (width of receive Frame Sync
                                     * (3-2)   Reserved
                                     * (1)     FSRM    - Internally-generated receive frame sync
                                     * (0)     FSRP    - A failling edge (for I2S) indicates beginning of frame */
    /* .rtdm     = */ 0x00000003, /* Receive TDM Time Slot Register
                                     * only 2 slots active (for I2S)       */
    /* .rintctl = */ 0x00000003, /* Receiver Interrupt Control Register
                                     * underrun and sync error active (For now, might need change in future)      */
    /* .rstat    = */ 0x000001FF, /* Receiver Status Register
                                     * reset any existing status bits      */
    /* .revtctl = */ 0x00000000, /* Receiver DMA Event Control Register
                                     * DMA mode                            */
    {
         /* .aclkrctl = */ 0x0000003F, /* Receive Clock Control Register,
                                          * (31-8) Reserved
                                          * (7)    CLKRP    - Falling edge. (don't know what it means)
                                          * (6)    Reserved
                                          * (5)    CLKRM    - internal
                                          * (4-0) CLKRDIV    - divide by 32 */
         /* .ahclkrctl = */ 0x0000000F, /* Receive High-Frequency Clock Control Register
                                          * external, divide-by-16                     */
         /* .rclkchk   = */ 0x00000000   /* Receive Clock Check Control Register      */

    }
};

1) When I measure the Master Clock using Scope, it shows the frenquency is about 24.5. However, the Bit clock is about the same with Master Clock, which should be 32 times slower. Did I do something wrong here?

2) For receive data, I created SIO stream

sioAttrs       = SIO_ATTRS;
    sioAttrs.nbufs = numOfBufs;
    sioAttrs.align = BUFALIGN;
    sioAttrs.model = SIO_ISSUERECLAIM;
    sioAttrs.timeout = 10000;

    /* open the I/O streams for input only */
    inStream = SIO_create("/dioMcaspIN", SIO_INPUT, BUFLEN, &sioAttrs);// BUFSIZE, &sioAttrs);

I was told by an Electronics Engineer that if the McASP is set up correctly(as mentioned above), I should see output data even the data might not be meanful. But SIO_reclaim() always return nmadus with value -9. This makes the actual Error Code 9, but I couldn't find anywhere what it means.

The tools that I am using:

CCS V4.2.1.00004

BIOS 5_41_10_36

EDMA edma3_lld_01_10_00_01 (Also tried edma3_lld_01_11_02_05)

pspdrivers_01_30_01

Any suggestion will be appreciated.

Regards,

Sarah

over 14 years ago

0 dabuan over 14 years ago

TI__Genius 14545 points

Sarah,

Sarah Zhang said:
1) When I measure the Master Clock using Scope, it shows the frenquency is about 24.5. However, the Bit clock is about the same with Master Clock, which should be 32 times slower. Did I do something wrong here?

You can refer to the McASPEcho project in the quickStartOMAPL1x_rCSL Program for code that configures the McASP to a 2 Channel I2S. Specifically refer to mcasp.c in the package.

The McASP requires a specific initialization sequence as specified in the OMAP-L138 McASP User's Guide. You can use this guide to follow along with the code provided in mcasp.c

Sarah Zhang said:
I was told by an Electronics Engineer that if the McASP is set up correctly(as mentioned above), I should see output data even the data might not be meanful. But SIO_reclaim() always return nmadus with value -9. This makes the actual Error Code 9, but I couldn't find anywhere what it means.

No necessarily true. The McASP has a feature implemented in hardware in which the AXR pins will not output any data low (is driven logic low) during an McASP Transmit under run condition. In this case, the output will remain muted until the under run condition is resolved, so you won't see any data output to the pin.

The error codes for DSP/BIOS 5 can be found in the DSP/BIOS 5 API Reference Guide

0 Sarah Zhang over 14 years ago in reply to dabuan

Prodigy 130 points

Hi Drew,

Thank you for your reply.

I did refer to the McASPEcho project to configure and initialise the McASP. The code in McASPEcho project is well documented and clear. But I found myself lost again once I came to use PSP BIOS.

Take McASPSampleMaster project in pspdrivers_01_30_01 for example

1) There is this 'mcaspParams' in mcaspSampleMaster_main.c. It provides the access to set the McASP Clocks, Data pin direction and Data Format. And there is 'Mcasp_HwSetupData', which is used for the Mcasp_ChanParams setting, in mcaspSampleMaster_io.c. 'Mcasp_HwSetupData' also have McASP clocks and Data Format setting.

Are they the same thing and only need to be set once? If no, then which is the once that I need to use (in order to configure McASP to a 2 channel I2S)?

After my last post, I assumed that 'mcaspParams' is for Device global data and 'Mcasp_HwSetupData' is for the channel instance. So I set both of them, still no luck.

2) If SIO_reclaim() returns with error code 9, what is the error information? Or where am I able to find this information?

Thanks,

Sarah

0 dabuan over 14 years ago in reply to Sarah Zhang

TI__Genius 14545 points

Sarah

Sarah Zhang said:
Are they the same thing and only need to be set once?

Clocks only need to be set up once. I'm not familiar with the BIOS PSP driver. I suggest that you re-post this question in the BIOS forum.

Sarah Zhang said:
If SIO_reclaim() returns with error code 9, what is the error information? Or where am I able to find this information?

Error codes for DSP/BIOS can be found in the the DSP/BIOS API Reference Guide

Processors

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McASP Receive Bit Clock Set up