DRA829V: How to use CCS to debug code on r5f with a72 already running QNX?

Hello,

I will bring this thread to the attention of the device experts. They will be able to guide you further.

Thanks

ki

Hi,

CCS is capable of connecting to the R5 and debugging without effecting the A72 regardless of the A72 HLOS that is running.   

The contents of the js file and steps being followed would need to be understood, to provide any feedback on why the A72 is being affected.

Regards,

kb

I have tried following the following chapter of the manual: 7.4. Debugging with HLOS running on A72 (Linux / QNX). When CCS is ready I can't connect to MCU2_0 which I intend to debug. I can only connect to MCU1_0.

Hi,

Still not clear on overall setup / instructions being followed, but will make some assumptions

Assumptions:

• Board is booting, via SD boot, or some other boot mode, and all cores that are desired are running, without CCS connected.
• Desire is to then attach to a particular core with CCS, without having any effect on other cores or the system in general.

If above bullets are true, then reference PSDK 8.1 documentation, ,Section 8.4,  8. CCS Setup for J721E — Processor SDK QNX J721E (ti.com)

Once the CCS is connected to the target, and the configuration launched, you should be able to right click on any core to connect.

Note, that the steps in previous section 8.3 8. CCS Setup for J721E — Processor SDK QNX J721E (ti.com) must not be run.  Please check your CCS setup to ensure that

• The GEL file as is stated in 8.3.1 is not present.  The DMSC is already running no need to run the GEL file.
• The launch script in section 8.3.2 is not being run.   It is not required.  The launch.js is for when the EVM is in No Boot mode. 

Please advise if this helps, or assumptions are incorrect.

Regards,

kb

HI, KB

My board boots via EMMC. The A72 was running successfully before I tested CCS. This has been confirmed by my colleagues in charge of A72 software development. I have followed section 8.4 to set up CCS. I did not refer to section 8.3, and did not use GEL files or launch scripts. When CCS is ready I can only connect A72 core0 or MCU R5F core0. Other cores cannot be connected.

Thank you for the details,

This thread started with "debug r5f with CCS without disturbing the A72", is this now functional?

Regarding the connecting to the other cores, does the MCUR5F  boot log indicate that the cores such as the MAIN R5f have been loaded successfully?

Regards,

kb

No, it doesn't work yet. I can only follow section 8.3 to start debugging on MCU2_0. This causes the running OS on the A72 to break when the gel and js files are loaded.

For the second question, after loading the Target Configuration File, there is no log displayed on CCS. I will connect MCU2_0 directly as described in Section 8.4, then CCS will report that it cannot be connected.

Hi,

Why are Gel and JS files being loaded? 

Given that your board is booting from eMMC, the CCS should be able to connect to the A72 or R5 core, on the running system, without the need for GEL and JS.

Regards,

kb

In fact, after the A72 is booted from emmc I can't connect to MCU2_0 without loading the gel or js files. That's why I asked for help at E2E.

Hi,

Okay, so the issue under debug is:

• When booting from eMMC, unable to connect to MCU2_0 using CCS.

Can you please provide any/all of the boot logs that are available.  In all likely hood the MCU2_0 core has:

1) Not been loaded/started

2) Hit an error condition

Regarding (1), the hope is that the boot log will have an error log, or hint as to why MCU2_0 was not started

Regarding (2),

• has the same MCU2_0 image been validated in a different boot mode
• has a simplified MCU2_0 image that is known to work been loaded from a different boot mode, and loaded from eMMC boot mode.

Is SBL or SPL boot being used in the system under test?

Thanks,

kb

The following is the complete boot log. I didn't find anything that might affect MCU2_0.

U-Boot SPL 2020.01-00002-g4805fecf28-dirty (Sep 20 2021 - 09:30:13 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Trying to boot from MMC1
Loading Environment from MMC... *** Warning - bad CRC, using default environment

init_env from device 17 not supported!
Starting ATF on ARM64 core...

NOTICE: BL31: v2.4(release):07.03.00.005-dirty
NOTICE: BL31: Built : 11:11:12, Aug 19 2021

U-Boot SPL 2020.01-00002-g4805fecf28-dirty (Sep 20 2021 - 09:31:08 +0530)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Trying to boot from MMC1

U-Boot 2020.01-00002-g4805fecf28-dirty (Sep 20 2021 - 09:31:08 +0530)

SoC: J721E SR1.0
Model: Texas Instruments K3 J721E SoC
DRAM: 1 GiB
Flash: 0 Bytes
MMC: sdhci@4f80000: 0, sdhci@4fb0000: 1
Loading Environment from MMC... OK
In: serial@2800000
Out: serial@2800000
Err: serial@2800000
Net: K3 CPSW: nuss_ver: 0x6BA00101 cpsw_ver: 0x6BA80100 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
eth0: ethernet@46000000
Hit any key to stop autoboot: 2 1 0
switch to partitions #0, OK
mmc0(part 0) is current device
SD/MMC found on device 0
599 bytes read in 1 ms (585 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
Core 1 is already in use. No rproc commands work
Core 2 is already in use. No rproc commands work
1988416 bytes read in 44 ms (43.1 MiB/s)
Load Remote Processor 2 with data@addr=0x80080000 1988416 bytes: Success!
11483328 bytes read in 245 ms (44.7 MiB/s)
## Starting application at 0x80080000 ...
MMU: 16-bit ASID 44-bit PA TCR_EL1=b5183519
ARM GIC-500 r1p1, arch v3.0 detected
gic_v3_lpi_add_entry for vectors 8192 -> 8447, Ok
gic_v3_lpi_add_entry for vectors 8448 -> 65535, Ok
No SPI intrinfo. Add default entry for 32 -> 991 vectors, Ok
LPI config table #1 @ 000000008000f000, callout vaddr: ffffff8040251000
cpu0: MPIDR=80000000
cpu0: MIDR=411fd080 Cortex-A72 r1p0
cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu0: L1 Icache 48K linesz=64 set/way=256/3
cpu0: L1 Dcache 32K linesz=64 set/way=256/2
cpu0: L2 Unified 1024K linesz=64 set/way=1024/16
Enabling ITS 0
ITS queue at 0000000080020000, num slots: 256
Issue MAPC/SYNC/INVALL commands for ICID 0
update CWRITER to 0x00000060
Waiting for all commands to be processed ... Done in 1 tries
Enable LPIs in GICR_CTLR @ 0000000001900000 for CPU0
Loading IFS...decompressing...done
cpu1: MPIDR=80000001
cpu1: MIDR=411fd080 Cortex-A72 r1p0
cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 PIPT
cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1
cpu1: L1 Icache 48K linesz=64 set/way=256/3
cpu1: L1 Dcache 32K linesz=64 set/way=256/2
cpu1: L2 Unified 1024K linesz=64 set/way=1024/16
ITS 0 already Enabled
ITS queue at 0000000080020000, num slots: 256
Issue MAPC/SYNC/INVALL commands for ICID 1
update CWRITER to 0x000000c0
Waiting for all commands to be processed ... Done in 1 tries
Enable LPIs in GICR_CTLR @ 0000000001920000 for CPU1

System page at phys:0000000080023000 user:ffffff8040275000 kern:ffffff8040272000
Starting next program at vffffff8060096e10
All ClockCycles offsets within tolerance
Welcome to QNX Neutrino 7.1.0 on the Nexus OnCore TI J721E Board!!
Starting random service ...
Starting TI services ...
Starting TI IPC Resmgr
start serial driver
Starting Serial driver (/dev/ser3)... RS485 port 9
Setting OS clock from RTC
omap_i2c_wait_status: PID_13 Connection timed out(260), dev->status 0, stat reg 1000
RTC: bq32002_i2c_read() failed
Starting MMC/SD memory card driver... eMMC
Path=0 - am65x
target=0 lun=0 Direct-Access(0) - SDMMC: 008GB0 Rev: 0.4
Starting Flash driver...
(devf t1::f3s_flash_probe:277) Unable to properly identify any flash devices
GPIO0_9, module/0 inst/9 bank/0 mux_val/256
setting 0x600018 to 0x200
GPIO should now be high
GPIOPID 0x00600000 = 0x44832905
GPIO_PCR 0x00600004 = 0x00000001
GPIO_BINTEN 0x00600008 = 0x00000000
GPIO_DIR01 0x00600010 = 0xafc3f0ff
GPIO_OUT_DATA01 0x00600014 = 0x00000200
GPIO_SET_DATA01 0x00600018 = 0x00000200
GPIO_CLR_DATA01 0x0060001c = 0x00000200
GPIO_IN_DATA01 0x00600020 = 0x00000041
GPIO_SET_RIS_TRIG01 0x00600024 = 0x00000000
GPIO_CLR_RIS_TRIG01 0x00600028 = 0x00000000
GPIO_SET_FAL_TRIG01 0x0060002c = 0x00000000
GPIO_CLR_FAL_TRIG01 0x00600030 = 0x00000000
GPIO_INTSTAT01 0x00600034 = 0x00000000

GPIO0_10, module/0 inst/10 bank/0 mux_val/256
setting 0x600018 to 0x600
GPIO should now be high
GPIOPID 0x00600000 = 0x44832905
GPIO_PCR 0x00600004 = 0x00000001
GPIO_BINTEN 0x00600008 = 0x00000000
GPIO_DIR01 0x00600010 = 0xafc3f0ff
GPIO_OUT_DATA01 0x00600014 = 0x00000600
GPIO_SET_DATA01 0x00600018 = 0x00000600
GPIO_CLR_DATA01 0x0060001c = 0x00000600
GPIO_IN_DATA01 0x00600020 = 0x00000041
GPIO_SET_RIS_TRIG01 0x00600024 = 0x00000000
GPIO_CLR_RIS_TRIG01 0x00600028 = 0x00000000
GPIO_SET_FAL_TRIG01 0x0060002c = 0x00000000
GPIO_CLR_FAL_TRIG01 0x00600030 = 0x00000000
GPIO_INTSTAT01 0x00600034 = 0x00000000

GPIO0_18, module/0 inst/18 bank/1 mux_val/257
setting 0x600018 to 0x40600
GPIO should now be high
GPIOPID 0x00600000 = 0x44832905
GPIO_PCR 0x00600004 = 0x00000001
GPIO_BINTEN 0x00600008 = 0x00000000
GPIO_DIR01 0x00600010 = 0xafc3f0ff
GPIO_OUT_DATA01 0x00600014 = 0x00040600
GPIO_SET_DATA01 0x00600018 = 0x00040600
GPIO_CLR_DATA01 0x0060001c = 0x00040600
GPIO_IN_DATA01 0x00600020 = 0x00000041
GPIO_SET_RIS_TRIG01 0x00600024 = 0x00000000
GPIO_CLR_RIS_TRIG01 0x00600028 = 0x00000000
GPIO_SET_FAL_TRIG01 0x0060002c = 0x00000000
GPIO_CLR_FAL_TRIG01 0x00600030 = 0x00000000
GPIO_INTSTAT01 0x00600034 = 0x00000000

GPIO0_20, module/0 inst/20 bank/1 mux_val/257
setting 0x600018 to 0x140600
GPIO should now be high
GPIOPID 0x00600000 = 0x44832905
GPIO_PCR 0x00600004 = 0x00000001
GPIO_BINTEN 0x00600008 = 0x00000000
GPIO_DIR01 0x00600010 = 0xafc3f0ff
GPIO_OUT_DATA01 0x00600014 = 0x00140600
GPIO_SET_DATA01 0x00600018 = 0x00140600
GPIO_CLR_DATA01 0x0060001c = 0x00140600
GPIO_IN_DATA01 0x00600020 = 0x00000041
GPIO_SET_RIS_TRIG01 0x00600024 = 0x00000000
GPIO_CLR_RIS_TRIG01 0x00600028 = 0x00000000
GPIO_SET_FAL_TRIG01 0x0060002c = 0x00000000
GPIO_CLR_FAL_TRIG01 0x00600030 = 0x00000000
GPIO_INTSTAT01 0x00600034 = 0x00000000

Starting PCI Server...
Setting environment variables...
Mounting the emmc ..
Press ENTER key within 2 SECONDS to ABORT startup

No key pressed
Normal Startup
Starting Firmware

* Network Configuration Beginning
Slaying devc-pty
Starting network Driver ...
Starting TCP/IP mc0 with address 192.168.101.52 and netmask 255.255.255.0
Starting TCP/IP am0 with address 192.168.102.52 and netmask 255.255.255.0
Configuring TMR Route for 224.0.7.33 through iface (192.168.101.52)
add host 224.0.7.33: gateway 192.168.101.52
Configuring TMR Route for 224.0.7.34 through iface (192.168.102.52)
add host 224.0.7.34: gateway 192.168.102.52
Configuring TMR Route for 224.0.7.1 through iface (192.168.1.8)
route: writing to routing socket: Network is unreachable
add host 224.0.7.1: gateway 192.168.1.8: Network is unreachable
Configuring TMR Route for 224.0.7.35 through iface (192.168.1.8)
route: writing to routing socket: Network is unreachable
add host 224.0.7.35: gateway 192.168.1.8: Network is unreachable
Configuring TMR Route for 232.0.1.1 through iface (192.168.1.8)
route: writing to routing socket: Network is unreachable
add host 232.0.1.1: gateway 192.168.1.8: Network is unreachable
Configuring TMR Route for 224.0.7.2 through iface (192.168.2.8)
route: writing to routing socket: Network is unreachable
add host 224.0.7.2: gateway 192.168.2.8: Network is unreachable
Configuring TMR Route for 224.0.7.36 through iface (192.168.2.8)
route: writing to routing socket: Network is unreachable
add host 224.0.7.36: gateway 192.168.2.8: Network is unreachable
Configuring TMR Route for 224.0.7.3 through iface (192.168.3.8)
route: writing to routing socket: Network is unreachable
add host 224.0.7.3: gateway 192.168.3.8: Network is unreachable
Configuring TMR Route for 224.0.7.37 through iface (192.168.3.8)
route: writing to routing socket: Network is unreachable
add host 224.0.7.37: gateway 192.168.3.8: Network is unreachable
* Network Configuration Complete
SDP: Mask changed from 0 to 33
UDH0 IP=0xC0A86534
sdp - Listen on SDI server port ready.
1 Jan 00:00:10 ntpd[364570]: ntpd 4.2.8p15@1.3728-o Mon Aug 17 17:31:24 UTC 2020 (1): Starting
1 Jan 00:00:10 ntpd[364570]: Command line: ntpd -Af/LOG/ntp.drift -c /usr/app/active/ntp.conf -gn -P17
1 Jan 00:00:10 ntpd[364570]: ----------------------------------------------------
1 Jan 00:00:10 ntpd[364570]: ntp-4 is maintained by Network Time Foundation,
1 Jan 00:00:10 ntpd[364570]: Inc. (NTF), a non-profit 501(c)(3) public-benefit
1 Jan 00:00:10 ntpd[364570]: corporation. Support and training for ntp-4 are
1 Jan 00:00:10 ntpd[364570]: available at https://www.nwtime.org/support
1 Jan 00:00:10 ntpd[364570]: ----------------------------------------------------
Read MarkVIe Nexus node table...
1 Jan 00:00:10 ntpd[364570]: proto: precision = 1000.000 usec (-10)
1 Jan 00:00:10 ntpd[364570]: proto: fuzz beneath 0.088 usec
1 Jan 00:00:11 ntpd[364570]: basedate set to 2020-08-05
1 Jan 00:00:11 ntpd[364570]: gps base set to 2020-08-09 (week 2118)
1 Jan 00:00:11 ntpd[364570]: Listen and drop on 0 v6wildcard [::]:123
1 Jan 00:00:11 ntpd[364570]: Listen and drop on 1 v4wildcard 0.0.0.0:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 2 lo0 127.0.0.1:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 3 lo0 [::1]:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 4 lo0 [fe80::1%1]:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 5 am0 [fe80::e615:f6ff:fe53:2112%17]:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 6 am0 192.168.102.52:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 7 mc0 [fe80::3ec2:e1ff:fe00:7001%18]:123
1 Jan 00:00:11 ntpd[364570]: Listen normally on 8 mc0 192.168.101.52:123
1 Jan 00:00:11 ntpd[364570]: Listening on routing socket on fd #25 for interface updates
Welcome using OptimumC Control software 1.0
VDPU: Mask changed from 0 to 33
There are 5 network interfaces in the controller!
====================================================================
DevNameofEn[0]=mc0 DevNameofEn[1]=mc1
DevNameofEn[2]=wm6 DevNameofEn[3]=wm6
DevNameofEn[4]=am0
====================================================================
Failed to call GetModuleFileName!
mc0 mask: 0xFFFFFF00
am0 mask: 0xFFFFFF00
EGD receives initresolver 385051, 1
EGD connect to APP(385051) InputData Channel(1) returns 1073741838
J7oncore# InitWatchDog InitWatchDog InitWatchDog
===================TimerInterruptThread_New====================
i=0 MyTraceNet[i].SysSock=9
i=4 MyTraceNet[i].SysSock=9
Sock=9
----UDH EGD PRODUCTION CONFIGURATION--
----UDH EGD PRODUCTION CONFIGURATION--,NUMS = 0

Thanks for providing the log,

If you stop the boot flow on the Uboot prompt are you able to connect to the MCU2_0 with CCS?

Regarding "anything that might affect MCU2_0", one possibility to consider is a memory conflict, between the memory that the MCU2_0 expects to run in, and the memory used by the A72 HLOS and applications.

Some things to check:

1) What memory does the MCU2_0 image, expect to be reserved for it.  This can be seen in the linker file for the R5 image (.lds), or if vision apps is being used, in the ${PSDK_RTOS_PATH}/vision_apps/apps/basic_demos/app_tirtos/tirtos_qnx/system_memory_map.html.

2) What is QNX view of available memory ranges?  Use "pidin syspage=asinfo", and/or look at the build file, (see 9.3. How To Take Care Of Remote Core Memory Map Updates — Processor SDK QNX J721E (ti.com))

3) What memory is being reserved for the PCI server.  This physical address ranges reserved for PCIe must not conflict with MCU2_0.

Regards,

kb