TDA4VM: [tivxAlgiVisionCreate:344] Calling ialg.algAlloc failed with status = -1110

Yao Wanchao

Part Number: TDA4VM

When converting on model, I got an error as shown in the title.

And full logs are show as below. So what is the reason and how to fix it?

$ python onenet_convert.py
tidl_tools_path = /home/wanchaoyao/Code/TexasInstruments/edgeai-tidl-tools/tidl_tools
artifacts_folder = custom-artifacts/onnx/onenet
tidl_tensor_bits = 8
debug_level = 3
num_tidl_subgraphs = 16
tidl_denylist = Transpose Reshape
tidl_calibration_accuracy_level = 64
tidl_calibration_options:num_frames_calibration = 1
tidl_calibration_options:bias_calibration_iterations = 3
power_of_2_quantization = 2
enable_high_resolution_optimization = 0
pre_batchnorm_fold = 1
add_data_convert_ops = 0
output_feature_16bit_names_list =
m_params_16bit_names_list =
reserved_compile_constraints_flag = 1601
ti_internal_reserved_1 =
Parsing ONNX Model
model_proto 0x7ffe4129c700

****** WARNING : Network not identified as Object Detection network - Ignore if network is not OD *****

Supported TIDL layer type --- Conv -- Conv_0
Supported TIDL layer type --- Relu -- Relu_1
Supported TIDL layer type --- MaxPool -- MaxPool_2
Supported TIDL layer type --- Conv -- Conv_3
Supported TIDL layer type --- Relu -- Relu_4
Supported TIDL layer type --- Conv -- Conv_5
Supported TIDL layer type --- Add -- Add_6
Supported TIDL layer type --- Relu -- Relu_7
Supported TIDL layer type --- Conv -- Conv_8
Supported TIDL layer type --- Relu -- Relu_9
Supported TIDL layer type --- Conv -- Conv_10
Supported TIDL layer type --- Add -- Add_11
Supported TIDL layer type --- Relu -- Relu_12
Supported TIDL layer type --- Conv -- Conv_13
Supported TIDL layer type --- Relu -- Relu_14
Supported TIDL layer type --- Conv -- Conv_15
Supported TIDL layer type --- Conv -- Conv_16
Supported TIDL layer type --- Add -- Add_17
Supported TIDL layer type --- Relu -- Relu_18
Supported TIDL layer type --- Conv -- Conv_19
Supported TIDL layer type --- Relu -- Relu_20
Supported TIDL layer type --- Conv -- Conv_21
Supported TIDL layer type --- Add -- Add_22
Supported TIDL layer type --- Relu -- Relu_23
Supported TIDL layer type --- Conv -- Conv_24
Supported TIDL layer type --- Relu -- Relu_25
Supported TIDL layer type --- Conv -- Conv_26
Supported TIDL layer type --- Conv -- Conv_27
Supported TIDL layer type --- Add -- Add_28
Supported TIDL layer type --- Relu -- Relu_29
Supported TIDL layer type --- Conv -- Conv_30
Supported TIDL layer type --- Relu -- Relu_31
Supported TIDL layer type --- Conv -- Conv_32
Supported TIDL layer type --- Add -- Add_33
Supported TIDL layer type --- Relu -- Relu_34
Supported TIDL layer type --- Conv -- Conv_35
Supported TIDL layer type --- Relu -- Relu_36
Supported TIDL layer type --- Conv -- Conv_37
Supported TIDL layer type --- Conv -- Conv_38
Supported TIDL layer type --- Add -- Add_39
Supported TIDL layer type --- Relu -- Relu_40
Supported TIDL layer type --- Conv -- Conv_41
Supported TIDL layer type --- Relu -- Relu_42
Supported TIDL layer type --- Conv -- Conv_43
Supported TIDL layer type --- Add -- Add_44
Supported TIDL layer type --- Relu -- Relu_45
Supported TIDL layer type --- Conv -- Conv_46
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_47
Supported TIDL layer type --- Conv -- Conv_48
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_49
Supported TIDL layer type --- Conv -- Conv_50
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_51
Supported TIDL layer type --- Conv -- Conv_52
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_53
Supported TIDL layer type --- Upsample -- Upsample_54
Supported TIDL layer type --- Add -- Add_55
Supported TIDL layer type --- Conv -- Conv_56
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_57
Supported TIDL layer type --- Upsample -- Upsample_58
Supported TIDL layer type --- Add -- Add_59
Supported TIDL layer type --- Conv -- Conv_60
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_61
Supported TIDL layer type --- Upsample -- Upsample_62
Supported TIDL layer type --- Add -- Add_63
Supported TIDL layer type --- Conv -- Conv_64
Supported TIDL layer type --- LeakyRelu -- LeakyRelu_65
Supported TIDL layer type --- Conv -- Conv_66
Supported TIDL layer type --- Relu -- Relu_67
Supported TIDL layer type --- Conv -- Conv_68
Supported TIDL layer type --- Conv -- Conv_69
Supported TIDL layer type --- Relu -- Relu_70
Supported TIDL layer type --- Conv -- Conv_71
Supported TIDL layer type --- Conv -- Conv_72
Supported TIDL layer type --- Relu -- Relu_73
Supported TIDL layer type --- Conv -- Conv_74
Supported TIDL layer type --- Conv -- Conv_75
Supported TIDL layer type --- Relu -- Relu_76
Supported TIDL layer type --- Conv -- Conv_77
Supported TIDL layer type --- Conv -- Conv_78
Supported TIDL layer type --- Relu -- Relu_79
Supported TIDL layer type --- Conv -- Conv_80
Supported TIDL layer type --- Conv -- Conv_81
Supported TIDL layer type --- Relu -- Relu_82
Supported TIDL layer type --- Conv -- Conv_83
Supported TIDL layer type --- Conv -- Conv_84
Supported TIDL layer type --- Relu -- Relu_85
Supported TIDL layer type --- Conv -- Conv_86
Supported TIDL layer type --- Conv -- Conv_87
Op type Reshape, TIDL layer type -- 39 added to unsupported nodes as specified in deny list
Unsupported layer 89 --- op type - Transpose, Number of input dims > 4 .. not supported by TIDL
Supported TIDL layer type --- Conv -- Conv_103
Op type Reshape, TIDL layer type -- 39 added to unsupported nodes as specified in deny list
Unsupported layer 92 --- op type - Transpose, Number of input dims > 4 .. not supported by TIDL
Supported TIDL layer type --- Conv -- Conv_119
Op type Reshape, TIDL layer type -- 39 added to unsupported nodes as specified in deny list
Unsupported layer 95 --- op type - Transpose, Number of input dims > 4 .. not supported by TIDL

Preliminary subgraphs created = 3
Final number of subgraphs created are : 1, - Offloaded Nodes - 90, Total Nodes - 96
Running runtimes graphviz - /home/wanchaoyao/Code/TexasInstruments/edgeai-tidl-tools/tidl_tools/tidl_graphVisualiser_runtimes.out custom-artifacts/onnx/onenet/allowedNode.txt custom-artifacts/onnx/onenet/tempDir/graphvizInfo.txt custom-artifacts/onnx/onenet/tempDir/runtimes_visualization.svg
In TIDL_createStateCommon
Compute on node : TIDLExecutionProvider_TIDL_0_0
0, Conv, 3, 1, input.1, 446
1, Relu, 1, 1, 446, 271
2, MaxPool, 1, 1, 271, 272
3, Conv, 3, 1, 272, 449
4, Relu, 1, 1, 449, 275
5, Conv, 3, 1, 275, 452
6, Add, 2, 1, 452, 278
7, Relu, 1, 1, 278, 279
8, Conv, 3, 1, 279, 455
9, Relu, 1, 1, 455, 282
10, Conv, 3, 1, 282, 458
11, Add, 2, 1, 458, 285
12, Relu, 1, 1, 285, 286
13, Conv, 3, 1, 286, 506
14, LeakyRelu, 1, 1, 506, 337
15, Conv, 3, 1, 286, 461
16, Relu, 1, 1, 461, 289
17, Conv, 3, 1, 289, 464
18, Conv, 3, 1, 286, 467
19, Add, 2, 1, 464, 294
20, Relu, 1, 1, 294, 295
21, Conv, 3, 1, 295, 470
22, Relu, 1, 1, 470, 298
23, Conv, 3, 1, 298, 473
24, Add, 2, 1, 473, 301
25, Relu, 1, 1, 301, 302
26, Conv, 3, 1, 302, 509
27, LeakyRelu, 1, 1, 509, 340
28, Conv, 3, 1, 302, 476
29, Relu, 1, 1, 476, 305
30, Conv, 3, 1, 305, 479
31, Conv, 3, 1, 302, 482
32, Add, 2, 1, 479, 310
33, Relu, 1, 1, 310, 311
34, Conv, 3, 1, 311, 485
35, Relu, 1, 1, 485, 314
36, Conv, 3, 1, 314, 488
37, Add, 2, 1, 488, 317
38, Relu, 1, 1, 317, 318
39, Conv, 3, 1, 318, 512
40, LeakyRelu, 1, 1, 512, 343
41, Conv, 3, 1, 318, 491
42, Relu, 1, 1, 491, 321
43, Conv, 3, 1, 321, 494
44, Conv, 3, 1, 318, 497
45, Add, 2, 1, 494, 326
46, Relu, 1, 1, 326, 327
47, Conv, 3, 1, 327, 500
48, Relu, 1, 1, 500, 330
49, Conv, 3, 1, 330, 503
50, Add, 2, 1, 503, 333
51, Relu, 1, 1, 333, 334
52, Conv, 3, 1, 334, 515
53, LeakyRelu, 1, 1, 515, 346
54, Upsample, 2, 1, 346, 350
55, Add, 2, 1, 343, 351
56, Conv, 3, 1, 351, 518
57, LeakyRelu, 1, 1, 518, 354
58, Upsample, 2, 1, 354, 358
59, Add, 2, 1, 340, 359
60, Conv, 3, 1, 359, 521
61, LeakyRelu, 1, 1, 521, 362
62, Upsample, 2, 1, 362, 366
63, Add, 2, 1, 337, 367
64, Conv, 3, 1, 367, 524
65, LeakyRelu, 1, 1, 524, 370
66, Conv, 3, 1, 370, 371
67, Conv, 3, 1, 370, 374
68, Conv, 3, 1, 370, 377
69, Conv, 3, 1, 370, 380
70, Relu, 1, 1, 380, 381
71, Conv, 3, 1, 381, 382
72, Conv, 3, 1, 370, 383
73, Relu, 1, 1, 383, 384
74, Conv, 3, 1, 384, 385
75, Conv, 3, 1, 370, 386
76, Relu, 1, 1, 386, 387
77, Conv, 3, 1, 387, 388
78, Conv, 3, 1, 370, 389
79, Relu, 1, 1, 389, 390
80, Conv, 3, 1, 390, 391
81, Conv, 3, 1, 362, 392
82, Reshape, 2, 1, 392, 410
83, Transpose, 1, 1, 410, 411
84, Conv, 3, 1, 354, 412
85, Reshape, 2, 1, 412, 430
86, Transpose, 1, 1, 430, 431
87, Conv, 3, 1, 346, 432
88, Reshape, 2, 1, 432, 444
89, Transpose, 1, 1, 444, 445

Input tensor name - input.1
Output tensor name - 445
Output tensor name - 431
Output tensor name - 411
Output tensor name - 391
Output tensor name - 388
Output tensor name - 385
Output tensor name - 382
Output tensor name - 377
Output tensor name - 374
Output tensor name - 371
0%| | 0/1 [00:00<?, ?it/s](1, 3, 576, 1024)
In TIDL_onnxRtImportInit subgraph_name=371374377382385388391411431445
Layer 0, subgraph id 371374377382385388391411431445, name=445
Layer 1, subgraph id 371374377382385388391411431445, name=431
Layer 2, subgraph id 371374377382385388391411431445, name=411
Layer 3, subgraph id 371374377382385388391411431445, name=391
Layer 4, subgraph id 371374377382385388391411431445, name=388
Layer 5, subgraph id 371374377382385388391411431445, name=385
Layer 6, subgraph id 371374377382385388391411431445, name=382
Layer 7, subgraph id 371374377382385388391411431445, name=377
Layer 8, subgraph id 371374377382385388391411431445, name=374
Layer 9, subgraph id 371374377382385388391411431445, name=371
Layer 10, subgraph id 371374377382385388391411431445, name=input.1
In TIDL_runtimesOptimizeNet: LayerIndex = 101, dataIndex = 91

************** Frame index 1 : Running float import *************
In TIDL_runtimesPostProcessNet
INFORMATION: [TIDL_ResizeLayer] Upsample_54 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
INFORMATION: [TIDL_ResizeLayer] Upsample_58 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
INFORMATION: [TIDL_ResizeLayer] Upsample_62 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
WARNING: [TIDL_E_DATAFLOW_INFO_NULL] ti_cnnperfsim.out fails to allocate memory in MSMC. Please look into perfsim log. This model can only be used on PC emulation, it will get fault on target.
****************************************************
** 4 WARNINGS 0 ERRORS **
****************************************************
************ in TIDL_subgraphRtCreate ************
0.0s: VX_ZONE_INIT:Enabled
0.19s: VX_ZONE_ERROR:Enabled
0.21s: VX_ZONE_WARNING:Enabled
0.935s: VX_ZONE_INIT:[tivxInit:178] Initialization Done !!!
TIDL_initDebugTraceParams Done
Alg Alloc for Layer # - 0
Alg Alloc for Layer # - 1
Alg Alloc for Layer # - 2
Alg Alloc for Layer # - 3
Alg Alloc for Layer # - 4
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Alg Alloc for Layer # - 60
Alg Alloc for Layer # - 61
Alg Alloc for Layer # - 62
Alg Alloc for Layer # - 63

TIDL Memory requiement
MemRecNum , Space , Attribute , SizeinBytes
0 , DDR , Persistent, 15208
1 , DDR , Persistent, 136
2 , L1D , Scratch , 16384
3 , L2 , Scratch , 1024
4 , L3/MSMC , Scratch , 57344
5 , DDR , Persistent, 58768
6 , DDR , Scratch , 172411776
7 , L1D , Scratch , 0
8 , DDR , Scratch , 154742912
9 , L1D , Scratch , 0
10 , L1D , Scratch , 0
11 , DDR , Persistent, 710656
12 , DDR , Scratch , 36992
13 , L1D , Scratch , 0
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
writeTraceLevel = 0

0.383749s: VX_ZONE_ERROR:[tivxAlgiVisionCreate:344] Calling ialg.algAlloc failed with status = -1110
0.383756s: VX_ZONE_ERROR:[tivxKernelTIDLCreate:656] tivxAlgiVisionCreate returned NULL
0.385525s: VX_ZONE_ERROR:[ownContextSendCmd:817] Command ack message returned failure cmd_status: -1
0.385553s: VX_ZONE_ERROR:[ownContextSendCmd:851] tivxEventWait() failed.
0.385564s: VX_ZONE_ERROR:[ownNodeKernelInit:538] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
0.385572s: VX_ZONE_ERROR:[ownNodeKernelInit:539] Please be sure the target callbacks have been registered for this core
0.385580s: VX_ZONE_ERROR:[ownNodeKernelInit:540] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
0.385591s: VX_ZONE_ERROR:[ownGraphNodeKernelInit:583] kernel init for node 0, kernel com.ti.tidl ... failed !!!
0.385602s: VX_ZONE_ERROR:[vxVerifyGraph:2055] Node kernel init failed
0.385609s: VX_ZONE_ERROR:[vxVerifyGraph:2109] Graph verify failed
TIDL_RT_OVX: ERROR: Verifying TIDL graph ... Failed !!!
TIDL_RT_OVX: ERROR: Verify OpenVX graph failed
************ TIDL_subgraphRtCreate done ************
******* In TIDL_subgraphRtInvoke ********
TIDL_initDebugTraceParams Done
Alg Alloc for Layer # - 0
Alg Alloc for Layer # - 1
Alg Alloc for Layer # - 2
Alg Alloc for Layer # - 3
Alg Alloc for Layer # - 4
Alg Alloc for Layer # - 5
Alg Alloc for Layer # - 6
Alg Alloc for Layer # - 7
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Alg Alloc for Layer # - 31
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Alg Alloc for Layer # - 33
Alg Alloc for Layer # - 34
Alg Alloc for Layer # - 35
Alg Alloc for Layer # - 36
Alg Alloc for Layer # - 37
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Alg Alloc for Layer # - 40
Alg Alloc for Layer # - 41
Alg Alloc for Layer # - 42
Alg Alloc for Layer # - 43
Alg Alloc for Layer # - 44
Alg Alloc for Layer # - 45
Alg Alloc for Layer # - 46
Alg Alloc for Layer # - 47
Alg Alloc for Layer # - 48
Alg Alloc for Layer # - 49
Alg Alloc for Layer # - 50
Alg Alloc for Layer # - 51
Alg Alloc for Layer # - 52
Alg Alloc for Layer # - 53
Alg Alloc for Layer # - 54
Alg Alloc for Layer # - 55
Alg Alloc for Layer # - 56
Alg Alloc for Layer # - 57
Alg Alloc for Layer # - 58
Alg Alloc for Layer # - 59
Alg Alloc for Layer # - 60
Alg Alloc for Layer # - 61
Alg Alloc for Layer # - 62
Alg Alloc for Layer # - 63

0.422714s: VX_ZONE_ERROR:[tivxAlgiVisionCreate:344] Calling ialg.algAlloc failed with status = -1110
0.422720s: VX_ZONE_ERROR:[tivxKernelTIDLCreate:656] tivxAlgiVisionCreate returned NULL
0.424424s: VX_ZONE_ERROR:[ownContextSendCmd:817] Command ack message returned failure cmd_status: -1
0.424441s: VX_ZONE_ERROR:[ownContextSendCmd:851] tivxEventWait() failed.
0.424450s: VX_ZONE_ERROR:[ownNodeKernelInit:538] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode
0.424458s: VX_ZONE_ERROR:[ownNodeKernelInit:539] Please be sure the target callbacks have been registered for this core
0.424466s: VX_ZONE_ERROR:[ownNodeKernelInit:540] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel
0.424477s: VX_ZONE_ERROR:[ownGraphNodeKernelInit:583] kernel init for node 0, kernel com.ti.tidl ... failed !!!
0.424486s: VX_ZONE_ERROR:[vxVerifyGraph:2055] Node kernel init failed
0.424493s: VX_ZONE_ERROR:[vxVerifyGraph:2109] Graph verify failed
0.424590s: VX_ZONE_ERROR:[ownGraphScheduleGraphWrapper:820] graph is not in a state required to be scheduled
0.424598s: VX_ZONE_ERROR:[vxProcessGraph:755] schedule graph failed
0.424605s: VX_ZONE_ERROR:[vxProcessGraph:760] wait graph failed
ERROR: Running TIDL graph ... Failed !!!
0.424625s: VX_ZONE_ERROR:[tivx_utils_tidl_trace_write:105] TIDL Trace Buffer empty
Sub Graph Stats 1716.000000 33614.000000 0.000000
******* TIDL_subgraphRtInvoke done ********

********** Frame Index 1 : Running fixed point mode for calibration **********
In TIDL_runtimesPostProcessNet

~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

Processing config file #0 : /home/wanchaoyao/Code/TexasInstruments/edgeai-tidl-tools/examples/jupyter_notebooks/custom-artifacts/onnx/onenet/tempDir/371374377382385388391411431445_tidl_io_.qunat_stats_config.txt
Error at line: 881 : in file /home/a0393754/work/c7x-mma-tidl/ti_dl/test/src/pc_linux/../tidl_rt.c, of function : TIDLRT_create
Error Type: TIDL_E_UNSUPPORTED_LAYER
Error at line: 452 : in file /home/a0393754/work/c7x-mma-tidl/ti_dl/test/src/pc_linux/../tidl_tb.c, of function : tidlMultiInstanceTest
Error Type: TIDL_E_UNSUPPORTED_LAYER

~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

***************** Calibration iteration number 0 completed ************************

~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

***************** Calibration iteration number 1 completed ************************

~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

***************** Calibration iteration number 2 completed ************************

------------------ Network Compiler Traces -----------------------------
successful Memory allocation
substitute string tidl_net_ not found
INFORMATION: [TIDL_ResizeLayer] Upsample_54 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
INFORMATION: [TIDL_ResizeLayer] Upsample_58 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
INFORMATION: [TIDL_ResizeLayer] Upsample_62 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
ERROR: TIDL_E_QUANT_STATS_NOT_AVAILABLE] tidl_quant_stats_tool.out fails to collect dynamic range. Please look into quant stats log. This model will get fault on target.
****************************************************
** 3 WARNINGS 1 ERRORS **
****************************************************
100%|█████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████████| 1/1 [00:21<00:00, 21.71s/it]
************ in TIDL_subgraphRtDelete ************
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over 4 years ago