C5504 interrupt preempting.

Hi,

Yes it's possible. If you are using BIOS, it'll make you easier than not using BIOS.

Regards,

Hyun

Hi Hyun:

Does that mean that interrupt preempting is not possible if I am not using the BIOS?

The reason I am asking is that we seem to be missing INT0 interrupts.

Suppose that we are inside a DMA isr and an INT0 interrupt occurs. Will the DMA interrupt be preempted and the INT0 isr will start executing?

Or, does the INT0 interrupt have to be enabled within the DMA isr for the INT0 interrupt to preempt the DMA isr?

Thanks a lot.

Cheers,

Mushtaq

What is happening is that when the ISR enters it turns off the global interrupt (INTM = 1).  See page 5-10, Figure 5.1 of the CPU guide http://focus.ti.com/lit/ug/swpu073e/swpu073e.pdf .  This means by default all ISRs are non preemptable by maskable interrupts.  However, to allow preemption (what RTOSes like BIOS do), you just simply have to re-enable the flag (INTM = 0) when you enter your ISR.

Tim

Hi Tim:

Thanks a lot!

I would like to continue this discussion further.

I enabling DMA3 channels and DMA event at the end of the INT0 isr (for data acquisition from FPGA via EMIF). I disable the DMA channels and DMA event at the end of the DMA isr. However, this seems to be messing up data acquisition. I no longer get INT0 interrupts. Since INT0 is a higher priority interrupt than the DMA interrupts, enabling DMA interrupt at the end of the INT0 isr should not cause any problems. Could you please shed some light on this?

Thanks a lot!

Cheers,

Mushtaq

As far as I believe, but I am not 100% sure, the priority system does not include the interrupt you are currently in.  This is because by default there is no preemption.  Thus when you are in your INT0 isr, and you get another ISR, the priority of the current one doesnt count.  The priority only matters if you get two new ones - from these two the highest priority will be chosen first.

However, I believe that due to the default non-preemptive system, interrupts will just be backed up behind each other i.e. if you get a DMA ISR while you are in INT0 with interrupts disabled, it should wait and immediately fire once you leave your INT0 isr.  This is unless there is another INT0 just around the corner.  If this is the case you are spending too much time in the interrupt / using too much CPU.

I will probably need some one from TI with more intimate knowledge to verify / contradict my theories but hopefully its a starting point.

Tim

Hi Tim:

Thanks a lot!

That is very helpful.

Thanks again.

Cheers,

Mushtaq

Hi Hyun:

If am in the INT0 isr and I enable a DMA3 channel and interrupt towards the end of the INT0 ISR and a DM3 interrupt occurs before I exit the INT0 isr, will the DMA3 interrupt be serviced before exiting from the INT0 isr or after the INT0 isr is done?

Thanks a lot.

Cheers,

Mushtaq