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We are using am6548 and PSDK 08.01.00.03 Linux-RT.
We need to connect two ethernet switches (XRS700x) via RGMII to the processor. We have allocated two PRU ICSSG to do this. We set the parameter "phy-mode" = "rgmii" in the dtb. In this case, transmission works (frames are visible on the remote side), but reception does not work (there is no data in the system from the PRU ICSSG, but it is visible on the RGMII lines between the switch and the processor). This switch assumes a clock delay of 1.5-2 ns on the PHY side.
We increased the length of the RX_CLK line by 30 cm. And it helped - the data is transferred in both directions.
Does the PRU ICSSG (or its firmware) support RX_CLK delay setting? Is it possible to support this setting?
