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L2 Preload engine (PLE) example or documentation

Scott Best
Prodigy 50 points


 

Heyaz. Am looking at the Cortex A8 architecture description here:

http://processors.wiki.ti.com/index.php/Cortex-A8_Architecture

At the bottom, it reads "PLE is not the same Dynamic Memory Allocation (DMA) engine used in previous ARM family of processors but has a similar programming interface" I guess I'm looking for some documentation of the PLE programming interface.

Specifically, I'm trying to copy the contents of a specific L2 cache way that's been locked down. The usual L2 system array debug data registers do not seem to be enabled on this OMAP platform, as is mentioned in other posts, such as this one:

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/99358/347781.aspx#347781

Any pointers appreciated.

-Scott

  • 0
    TI__Expert 5960 points

    Scott,

    Have you looked at the Cortex-A8 TRM yet?  There is information on the PLE in there. You can search for that document here: http://infocenter.arm.com/help/index.jsp

    But you need to know which revision of Cortex-A8 processor you have: http://processors.wiki.ti.com/index.php/How_to_Find_the_Cortex-A8_Revision_of_your_OMAP35x

    Their are multiple sections with PLE information, but a bulk of the information can be found in the Chapter 3 - System Control Coprocessor.  Specifically look for the c9 and c11 definitions.

    If you are using Linux, then you can not access cache control, PLE and other "ARM Coprocessor" commands from application or user space which corresponds to user mode for ARM Cortex-A8.  You can only access these registers in kernel space which corresponds to supervisor mode for the ARM Cortex-A8.

  • 0 in reply to Jeff L
    Prodigy 50 points

    Jeff:

    Hello! Thanks for posting and for the pointer; I've been looking over the description of the C11 register in the TRM and I think what I want to try is this:

    1. Select one of the PLE channels to use (c11's c2)
    2. Set the "start of virtual address" I want to copy the L2 cache way contents into (c11's c5)
    3. Set the "end address" to be the size of the cache way (c11's c7)
    4. Set the control register to indicate a copy of the specific cache way (c11's c4)
    5. Start the copy (c11's c3)
    6. Check the status and loop until complete (c11's c8)

    Will try that approach soon; I've been unable to discover any instructive examples despite much Google'ing.

    Am slightly unsure about step #4, as the DT field ("direction of transfer") indicates a "a cache clean-and-invalidate operation" will be performed after I read the locked-down cache way. I'm not sure which will win: the locked status I've affected onto this cache way, or the clean-and-invalidate operation after using the PLE. Will know soon, I suppose...

    Finally, yes, we're writing this as a kernel module for the necessary privilege elevation; that was required to get the lockdown working.

    cheers,

    Scott

  • 0 in reply to Scott Best
    TI__Expert 5960 points

    Scott,

    There is no way to get clean data out of the L2, other than to invalidate the line via

    cache maintenance op .

    With the PLE control DT bit=1, the dirty data will be written out to memory and invalidated in

    L2 (r3p0 and beyond, or left as clean in L2 until r2p2). Clean lines will continue to remain valid.

     

    If coherency is the issue, then doing a final invalidate of the L1 + L2 will guarantee that any future

    program access to the data will generate a fetch from DDR.