Hello DSP BIOS Champs!!
CCS Version: CCSV4 ( Version: 4.2.1.00004 )
Target: TMS320F28335 (eZDSP from Spectrum Digital)
Emulators: XDS510 USB and XDS100v2
Software Package: spra958i.zip (from TI)
Application: \spra958i\spra958i\CCSv4\F28335_examples_CCSv4_2010Aug10\F28335_example_BIOS_flash
Problem Summary:
I am looking at the results.htm released with bios_5_41_07_24. Using the application stated above if I use the
CCS benchmark counter (Target->Clock-Enable), the count reported from the SWI_post to the actual function is
about 1773 clock cycles. The benchmark results, for a SWI_post, documented in the results.htm file are as follows:
| SWI_post: Hardware interrupt to software interrupt | 355 |
| SWI_enable | 29 |
| SWI_disable | 11 |
| SWI_post: Post software interrupt again | 36 |
| SWI_post: Post software interrupt, no context switch | 84 |
| SWI_post: Post software interrupt, context switch | 206 |
Why is there such a large discreapancy in the number of cycles?
Note that there is one other user defined function, which is a periodic function (LedBlink) but that was disabled, for this test.
So on the surface, it appears that only one ISR AdcSwi is enabled in this application.
Also note that RTDX is also disabled in order to enable the benchmark capability in CCS
Can you please advice...I believe that due to the intrusive nature of the benchmark counter, the count could be off by a few (10's) cycles.
But I would not expect it to be over a 1000 cycles...Please let me know if there are any other background tasks that DSP-BIOS is running
Thanks,
Krishna
