• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 969 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DP83867IR: Not able to perform 10 Mbps auto-negotiation

AM6548: DP83867 Cannot ping as well at 10Mbps speed

Eric Hsieh4
Expert 1300 points
Part Number: AM6548

Hi Ti,

We are using Linux RT SDK 07.01.00.18 on our customized board and tried to make a link to DP83867 at 10Mbps.

According to the link below, we check the register 0x0000[8] with full duplex enabled, and 0x004[0] set with 802.3u enabled. 

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/933842/dp83867ir-not-able-to-perform-10-mbps-auto-negotiation

Below is the register value we read at kernel dp83867_config_init()

BMCR: 0x1140

ANAR: 0x1e1

But after boot into OS, and we tried to dump the register, 

reg i=0 val=0x1140
reg i=1 val=0x796D
reg i=2 val=0x2000
reg i=3 val=0xA231
reg i=4 val=0x0111
reg i=5 val=0xCDE1
reg i=6 val=0x006D
reg i=7 val=0x2001
reg i=8 val=0x6001
reg i=9 val=0x0200
reg i=a val=0x7800
reg i=b val=0x0000
reg i=c val=0x0000
reg i=d val=0x401F
reg i=e val=0x0007
reg i=f val=0x3000
reg i=10 val=0x5048
reg i=11 val=0xAC02
reg i=12 val=0x0000
reg i=13 val=0x0000
reg i=14 val=0x29C7
reg i=15 val=0x0000
reg i=16 val=0x0000
reg i=17 val=0x0040
reg i=18 val=0x1919
reg i=19 val=0x4444
reg i=1a val=0x0002
reg i=1b val=0x0000
reg i=1c val=0x0000
reg i=1d val=0x0000
reg i=1e val=0x0202
reg i=1f val=0x0000

it seems the register value of ANAR has changed.

Out dts setting is as below:

/* Dual Ethernet application node on PRU-ICSSG1 */
pruss1_eth: pruss1_eth {
compatible = "ti,am654-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&ethernet0_pins_default>;
sram = <&msmc_ram>;
prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>,
<&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";

ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
mii-g-rt = <&icssg1_mii_g_rt>;
mii-rt = <&icssg1_mii_rt>;
dma-coherent;
dmas = <&main_udmap 0xc200>, /* egress slice 0 */
<&main_udmap 0xc201>, /* egress slice 0 */
<&main_udmap 0xc202>, /* egress slice 0 */
<&main_udmap 0xc203>, /* egress slice 0 */
<&main_udmap 0xc204>, /* egress slice 1 */
<&main_udmap 0xc205>, /* egress slice 1 */
<&main_udmap 0xc206>, /* egress slice 1 */
<&main_udmap 0xc207>, /* egress slice 1 */

<&main_udmap 0x4200>, /* ingress slice 0 */
<&main_udmap 0x4201>, /* ingress slice 1 */
<&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
<&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";

pruss1_emac0: ethernet-mii0 {
phy-handle = <&pruss1_eth0_phy>;
phy-mode = "rgmii-rxid";
interrupts-extended = <&icssg1_intc 24>;
syscon-rgmii-delay = <&scm_conf 0x4110>;
iep = <&icssg1_iep0>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};

pruss1_emac1: ethernet-mii1 {
phy-handle = <&pruss1_eth1_phy>;
phy-mode = "rgmii-rxid";
interrupts-extended = <&icssg1_intc 25>;
syscon-rgmii-delay = <&scm_conf 0x4114>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};

Could anyone help this?

Thanks.

Eric

  • 0
    Expert 1300 points

    Hi Ti,

    Anyone can help this?

    Eric

  • 0 in reply to Eric Hsieh4
    TI__Mastermind 23125 points

    Eric, 

    there was some reported issues on this and was fixed in SDK8.1. Are you restricted to SDK7.1 on your board? if not, we can update to SDK8.2. I can look details of the exact fix.

    Jian

  • 0 in reply to jian35385
    Expert 1300 points

    Hi ,

    Yes, we still on SDK7, could you share us the detail of the fix?

    Eric

  • 0 in reply to Eric Hsieh4
    Expert 1300 points

    Hi

    Any update?

    Eric

  • 0 in reply to Eric Hsieh4
    Expert 1300 points

    Hi ,

    While I testing this again, I also find it also cannot work at 100Mbps Half Duplex.

    So this issue happened with 10Mbps and 100Mbps half duplex.

    Below are registers dump:

    Case 1: work well

    reg i=0 val=0x1140
    reg i=1 val=0x796D
    reg i=2 val=0x2000
    reg i=3 val=0xA231
    reg i=4 val=0x0101
    reg i=5 val=0xCDE1
    reg i=6 val=0x006F
    reg i=7 val=0x2001
    reg i=8 val=0x6001
    reg i=9 val=0x0200
    reg i=a val=0x3800
    reg i=b val=0x0000
    reg i=c val=0x0000
    reg i=d val=0x401F
    reg i=e val=0x0007
    reg i=f val=0x3000
    reg i=10 val=0x5048
    reg i=11 val=0xAC02
    reg i=12 val=0x0000
    reg i=13 val=0x1C00
    reg i=14 val=0x2BC7
    reg i=15 val=0x0000
    reg i=16 val=0x0000
    reg i=17 val=0x0040
    reg i=18 val=0xCBCB
    reg i=19 val=0x4444
    reg i=1a val=0x0002
    reg i=1b val=0x0000
    reg i=1c val=0x0000
    reg i=1d val=0x0000
    reg i=1e val=0x0202
    reg i=1f val=0x0000

    Case 2: 10Mbps

    reg i=0 val=0x1140
    reg i=1 val=0x7949
    reg i=2 val=0x2000
    reg i=3 val=0xA231
    reg i=4 val=0x0101
    reg i=5 val=0x4C61
    reg i=6 val=0x0066
    reg i=7 val=0x2001
    reg i=8 val=0x0000
    reg i=9 val=0x0200
    reg i=a val=0x0000
    reg i=b val=0x0000
    reg i=c val=0x0000
    reg i=d val=0x401F
    reg i=e val=0x0007
    reg i=f val=0x3000
    reg i=10 val=0x5048
    reg i=11 val=0x0002
    reg i=12 val=0x0000
    reg i=13 val=0x9440
    reg i=14 val=0x2BC7
    reg i=15 val=0x0000
    reg i=16 val=0x0000
    reg i=17 val=0x0040
    reg i=18 val=0xCBCB
    reg i=19 val=0x4444
    reg i=1a val=0x0002
    reg i=1b val=0x0000
    reg i=1c val=0x0000
    reg i=1d val=0x0000
    reg i=1e val=0x0202
    reg i=1f val=0x0000

    Please help this.

    Thanks.

    Eric

  • 0 in reply to Eric Hsieh4
    TI__Mastermind 23125 points

    Eric, 

    can you try attached patch:

    /cfs-file/__key/communityserver-discussions-components-files/791/am65_5F00_s20_5F00_hd_5F00_patches.tar.xz

    Alternatively you can try the upstreamed:

    commit 7fd018ef244c981811e6662ce061eee03677e468
    Author: Grygorii Strashko <grygorii.strashko@ti.com>
    Date: Tue Oct 12 13:54:43 2021 +0300

    net: ethernet: icssg-prueth: sr2.0: add support for half duplex operation

    This patch adds support for half duplex operation at 10M and 100M link
    speeds for AM654x ICSS-G SR2.0 devices.

    • Driver configures rand_seed, a random number, in DMEM HD_RAND_SEED_OFFSET
      field, which will be used by firmware for Back off time calculation.
    • Driver informs FW about half duplex link operation in DMEM
      PORT_LINK_SPEED_OFFSET field by setting bit 7 for 10/100M HD.

    Hence, the half duplex operation depends on board design the
    "ti,half-duplex-capable" property has to be enabled for ICSS-G ports if HW
    is capable to perform half duplex.

    jian

  • 0 in reply to jian35385
    Expert 1300 points

    Hi ,

    I quickly check the patch files, and found there are 2 pins add in dts file.

    AM65X_IOPAD(0x026c, PIN_INPUT, 1) /* (AA28) PRG0_PRU1_GPO10.PRG0_PRU1_GPI10 - col */

    AM65X_IOPAD(0x021c, PIN_INPUT, 1) /* (U25) PRG0_PRU0_GPO10.pr0_mii0_crs */

    After check the DP83867 spec, these pins are not used for RGMII mode.

    Per the dts I provided, we are using RGMII mode.

    So, I want to check if there pins are necessary?

    Eric

  • 0 in reply to Eric Hsieh4
    Expert 1300 points

    Hi ,

    I tired with sdk 08_02_00_01, and found most of the patch you provide have already in.

    And I merge the 0002-net-ethernet-icssg-prueth-sr1.0-add-support-for-half.patch below and dts patch for half-duplex:

    + emac->half_duplex = of_property_read_bool(eth_node, "ti,half-duplex-capable");
    +
    /* remove unsupported modes */
    - phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
    - phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
    + if (!emac->half_duplex) {
    + phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
    + phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
    + }
    phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
    phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_Pause_BIT);
    phy_remove_link_mode(emac->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);

    The result is 10Mbps half-duplex still cannot work.

    Could you also help to check this?

    Thanks.

    Eric

  • 0 in reply to Eric Hsieh4
    TI__Mastermind 23125 points

    Eric, 

    I am checking with the development team on how the patch was tested. will add notes once i receive response. 

    regards

    Jian