TDA4VM: How to config DSS for BT601 output format?

Hi Huang, Golden,

Are you still looking for BT601 output format from the DSS? 

It is possible to get the output in BT601 format, but requires to use two Video Ports.. I can share the information, if you are interested. 

Regards,

Brijesh

Hi, Brijesh:

Of course, I am still looking for BT601 output format from the DSS.
Looking for your share more information.

Regards.

Hi Huang Golden,

Essentially we need to follow below steps to get the output in BT601 format, ie YUV422 in 8bit discrete sync format.

1. We need to use two Video ports, one configured in embedded sync format and other configured in discrete sync format. Then we use sync signals from the VP configured in discrete sync format and use data and clock from the VP configured in embedded sync format.
2. We would have to configure pinmux for vout0 data and sync signals correctly, such that sync signals are selected from the second VP. 
3. We need to configure pixel clock source for the VPs to the same PLL.. There are APIs in the SciClient which allows us to use same clock source.
4. We need to then ask driver to enable both the VPs at the same time. This makes sure that the data and syncs are generated in sync mode..  Driver provides interface syncOpCfg in Dss_DctrlVpParams to start the VPs at the same time.. 
5. We additionally also have to modify the blanking parameters for the VP configured in embedded sync output format to match with the VP in discrete sync format.. 
6. We can then connect any video pipeline to the VP configured in embedded sync format and get the BT601 output..

Regards,

Brijesh 

ok thanks Sancho.

Hi Brijesh,

I read section "12.6.2.1.4 VSYNC/HSYNC/DE Signal Export to SoC Boundary" in TRM and your suggestion.
I found "pdk_jacinto_07_03_00_29/packages/ti/drv/dss/examples/dss_display_test/" source code contain "DISP_APP_TEST_MULTISYNC" to config muti sync, which is consistent with your suggestion.
But there are some questions about the following points:

1. Am I right to config second VP in discrete sync format and enable both the VPs at the same time as below?

   vpParams->syncOpCfg.enabled = TRUE;
   vpParams->syncOpCfg.isPrimary = FALSE;
   vpParams->syncOpCfg.numSyncVpIds = 1U;
   vpParams->syncOpCfg.syncVpIds[0] = 1U;
   

2. What's the detail meaning of syncOpCfg.isPrimary?
3. I want to config VP1 as embedded sync format(8bits) and VP2 as discrete sync, which the value do I set in lcdOpTimingCfg.dvoFormat?
   FVID2_DV_BT656_EMBSYNC or FVID2_DV_GENERIC_DISCSYNC? Or do I need to set VP1 and VP2 separately?

Regards,

Sancho

Hi Sancho,

Sancho Huang said:

Am I right to config second VP in discrete sync format and enable both the VPs at the same time as below?

Set the parameters like below,

for VP outputting discrete sync

vpDsPrm->syncOpCfg.enabled = TRUE;
vpDsPrm->syncOpCfg.isPrimary = FALSE;
vpDsPrm->syncOpCfg.numSyncVpIds = 0U;

for VP outputting embedded sync

vpPrm->syncOpCfg.enabled = TRUE;
vpPrm->syncOpCfg.isPrimary = TRUE;
vpPrm->syncOpCfg.numSyncVpIds = 1U;
vpPrm->syncOpCfg.syncVpIds[0] = VP ID outputtting Discrete Sync;

Then first set VP parameters for discrete sync output and then VP parameters for embedded sync.

Sancho Huang said:

What's the detail meaning of syncOpCfg.isPrimary?

When this flag is set, this is when both the VPs will be enabled at the same time.

Sancho Huang said:

I want to config VP1 as embedded sync format(8bits) and VP2 as discrete sync, which the value do I set in lcdOpTimingCfg.dvoFormat?
FVID2_DV_BT656_EMBSYNC or FVID2_DV_GENERIC_DISCSYNC? Or do I need to set VP1 and VP2 separately?

VP parameters are different for both the VP and needs to be set independently, so first set the parameters for the VP outputting discrete sync, with dvoFormat set to FVID2_DV_GENERIC_DISCSYNC and then set the VP parameters for embedded sync..

Regards,

Brijesh

Regards,

Brijesh