66AK2L06: 66AK2L06 interface High Speeds ADCs and DACs

Hello!

JESD is a big thing. IF you have expertise in that area, you won't ask community. Otherwise that is a really hard thing. With the sample rates you mention I would go with FPGA as a glue logic.

Hello Joaquin,

Joaquin Lopez contreras said:

A second option is to use 6AK2L06 and the IQnet peripheral which it has 4 lines JESD204A/B and then use ADC/DAC with this serial port. ADC to use would be ADS42JB69 Dual-channel 16 bits, 250Msps, using only two of the JESD204 lines. For the DAC we are evaluating DAC37J82 16bit, 1.6GSPS and also only two JESD204 Lines. In the DAC case, the performance is much higher that what we need.

What do you think of this approach? Would it work? Do you see any problem? Could we have any problem to configure and operate the DAC at 100MSPS when it can be up to 1.6Gsps?. Any comment would be OK.

Unfortunately I don't have the technical expertise to offer any insights regarding this application with the 6AK2L06. You can consult with one of our third-party partners that are experienced with this device: https://e2e.ti.com/support/processors/f/791/t/809582 

That design support is coming from third-parties only is stated on the product page for this device and should be part of your consideration: https://www.ti.com/product/66AK2L06 

Joaquin Lopez contreras said:

First, we have evaluated to use TMSC320C6657 and the uPP peripheral. This uPP has two lines up to 75Mhz. We were thinking to use MAX5885 and ADC16V130. It would be OK if we only need one ADC and one DAC. But I dont see how we could connect two ADCs and two DACs. Beside, we would have 37.5Mhz as much for each device which is not acceptable. Do you agree with this? or is there any way to connect 4 devices to the uPP and keep the 75Mhz?

I will send this part of the query to another team who can speak to the TMSC320C6657 and its capabilities.

Best Regards,

Ralph Jacobi

Hi victor,

Thank you for your comment.

I case we would need a FPGA, What would be the best way to interface with a DSP? I mean, in one side we have the connections to ADC/DACs an at the other side the connection to a DSP. What interface/port would you recomemd to conect to a DSP?

Regards,

Joaquin.

Hi,

We have experience with C6670 operating together with AD9643 and AD9747. These two can run up to 250 MSPS, and have a parallel bus interface. Be sure running parallel interface at those speeds also requires certain efforts. We had to tune phase of the FPGA clock and use clock domain crossing FIFO to pull data in. It was certain amount of work, but doable with our prior experience. 66AK2L06 device has JESD port, which looks tempting. If you had an experience with it, than could consider as an option. What I could tell about us, we spent  many month attempting JESD interface and still in the very beginning of our way.

Things to keep in mind. With those simpler AD/DAs we have to perform baseband calibration. It includes several additions and multiplications. If you do that on DSP, it will consume whole processing power of your core. FPGA is doing that in our case sample by sample in realtime. Devices with JESD interfaces might have their internal hardware to perform such calibrations, that is for you to find.

Finally, if run AD/DA with parallel interfaces, then how to pull data into DSP. We are using PCIe interface. Keep in mind, that reading PCIe endpoint using processor in PIO mode will give about 40MBps on write, 2 MBps on read per gen1 lane. So if you have to process data in realtime, one have to use DMA. SoC side is relatively simple, we have EDMA3 here, then the question is to program it. However, on FPGA side one have to implement end point with DMA support. 7 series devices have IPs for that, in Spartan 6 it was 5 month project for me to implement DMA support.

Hi Victor,

Thank you very much for your support. I have read several times your comments to understand them at the maximum.

Probably we will contract a FPGA developer to help us on this system.

Again, thanks very much.

Joaquin.