question about PLL1

Pan,

   Have you tried to use the emulator to read back the registers to confirm that your settings get latched into the respective registers? This may give you some insight into why the PLL output is at a different frequency than what you expect.

Hi, Drew,

my question comes from the GEL file logicPD provides, so I wanna ask how the value was set and why the value is like that. I think there is nothing wrong with the hardware, just wanna find out WHY the values a set as is in GEL file.

Regards,

Power Pan

Pan,

   I'm not sure why Logic did this. You might want to submit a quest to the LogicPD support line to find out as they will probably know the reason since it was provided by their engineering staff.

Hi, Drew, 

if you suggest my sending e-mail to ask LogicPD, I'm going to forget the question because they still have my questions pending for some while and did not respond to my question. 

regards,

Power Pan

Pan,

   You could also use the OMAPL1x/AM1x /C674x PLL spreadsheet that we have available for the AM1x devices to determine the proper settings for the clocking registers. It might give you some insight into why they made the choices they did.