Status of SDOCM00067652: Suspend/resume doesn't succeed for 37x when off mode is enabled.

Hi Jeff,

The OFF mode should be supported in the PSP 03.00.01.06 now. I've just tried minimal configuration kernel image base on PSP 03.00.01.06 in low power standby wiki on the EVM. From PM_PREPWSTST register status in register dump by cat /debug/pm_debug/registers/2 command, I can see the processor is hitting to the OFF mode. I've also confirmed that VDD1 and VDD2 voltages have gone down on scope. This won't happen unless the processor goes to the OFF mode. Here is the procedure I tried with the image and pm_debug register dumps.  

[root@arago /]# mkdir /debug

[root@arago /]# mount -t debugfs debugfs /debug

[root@arago /]# echo 1 > /debug/pm_debug/sleep_while_idle

[root@arago /]# echo 1 > /debug/pm_debug/enable_off_mode

[root@arago /]# echo mem > /sys/power/state

PM: Syncing filesystems ... done.

Freezing user space processes ... (elapsed 0.02 seconds) done.

Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.

Suspending console(s) (use no_console_suspend to debug)

Successfully put all powerdomains to target state

Restarting tasks ... done.

[root@arago /]# cat /debug/pm_debug/registers/1

MOD: CM_IVA2 (48014000)

  04 => 00000017  20 => 00000001  34 => 00000001  40 => 00080a00

  44 => 00000001  48 => 00000003

MOD: CM_OCP (48004800)

  00 => 00000010  10 => 00000001

MOD: CM_MPU (48004900)

  04 => 00000037  24 => 00000001  34 => 00000001  40 => 00112c0c

  44 => 00000001  48 => 00000003  4c => 00000001

MOD: CM_CORE (48004a00)

  10 => 00000042  20 => ffffffbd  24 => 0000001f  28 => 0000000d

  30 => fffffed9  34 => 0000001f  38 => 0000000c  40 => 0000130a

  48 => 0000003f  4c => 00000003

MOD: CM_SGX (48004b00)

  20 => 00000001  40 => 00000005  48 => 00000003

MOD: CM_WKUP (48004c00)

  00 => 00000001  10 => 0000000d  20 => 000002f2  30 => 0000003f

  40 => 00000014

MOD: CM_CCR (48004d00)

  00 => 08310007  04 => 00000011  20 => 00000001  30 => 00000001

  34 => 00000001  40 => 08c80c00  44 => 0481b00c  48 => 00000009

  4c => 00003c0c  50 => 00000001  70 => 00000003

MOD: CM_DSS (48004e00)

  20 => 00000003  30 => 00000001  40 => 00001009  48 => 00000003

MOD: CM_CAM (48004f00)

  20 => 00000001  30 => 00000001  40 => 00000004  48 => 00000003

MOD: CM_PER (48005000)

  10 => 0003e000  20 => 00041fff  30 => 0003ffff  40 => 000000ff

  44 => 00000006  48 => 00000003  4c => 00000001

MOD: CM_EMU (48005100)

  40 => 03020a50  48 => 00000001

MOD: CM_NEON (48005300)

  48 => 00000003

MOD: CM_USB (48005400)

  20 => 00000003  30 => 00000001  48 => 00000003

MOD: PRM_IVA2 (48316000)

  50 => 00000007  e0 => 00ff0f04  f8 => 00000002

MOD: PRM_OCP (48306800)

  04 => 00000010  14 => 00000001  1c => 00000201

MOD: PRM_MPU (48306900)

  58 => 0000000c  d4 => 00000012  e0 => 00030104  e4 => 000000c7

  e8 => 000000c7

MOD: PRM_CORE (48306a00)

  58 => 00000304  a0 => c33ffe18  a4 => c33ffe18  e0 => 000f0314

  e4 => 000000f7  e8 => 000000f7  f0 => 00000004  f8 => 00000004

MOD: PRM_SGX (48306b00)

  e0 => 00030104

MOD: PRM_WKUP (48306c00)

  a0 => 0001010b  a4 => 0000010b  b0 => 00010000

MOD: PRM_CCR (48306d00)

  40 => 00000003

MOD: PRM_DSS (48306e00)

  a0 => 00000001  e0 => 00030104

MOD: PRM_CAM (48306f00)

  58 => 00000001  e0 => 00030104

MOD: PRM_PER (48307000)

  58 => 0000000c  a0 => 0003e807  a4 => 0003e807  c8 => 00000007

  e0 => 00030104  e4 => 00000007  e8 => 00000007

MOD: PRM_EMU (48307100)

  58 => 00000004  e4 => 00000100

MOD: PRM_GLBL (48307200)

  20 => 00120012  24 => 00010000  2c => 28201e00  30 => 2b201e00

  34 => 00120000  38 => 00000008  54 => 00001006  58 => 00000001

  60 => 00000004  64 => 00000050  70 => 00000048  90 => 0fff0fff

  94 => 000000ff  98 => 000000ff  9c => 00000002  a0 => 000000ff

  b0 => 00202808  b4 => 0001f401  b8 => 0001f404  bc => 3c00ffff

  c0 => 00000028  c4 => 00000001  d0 => 00202b08  d4 => 0001f401

  d8 => 0001f404  dc => 2c00ffff  e0 => 0000002b  e4 => 00000001

MOD: PRM_NEON (48307300)

  58 => 0000000c  c8 => 00000002  e0 => 00000004  e4 => 00000003

  e8 => 00000003

MOD: PRM_USB (48307400)

  58 => 00000008  a0 => 00000001  a4 => 00000001  a8 => 00000001

  e0 => 00030104

[root@arago /]# cat /debug/pm_debug/registers/2

MOD: CM_IVA2 (48014000)

  04 => 00000011  20 => 00000001  40 => 00080000  44 => 00000001

MOD: CM_OCP (48004800)

  00 => 00000010  10 => 00000001

MOD: CM_MPU (48004900)

  04 => 00000037  24 => 00000001  34 => 00000001  40 => 00112c0c

  44 => 00000001  4c => 00000001

MOD: CM_CORE (48004a00)

  10 => 0000004a  20 => ffffffbd  24 => 0000001f  28 => 0000000d

  30 => 00000008  40 => 0000130a  4c => 00000003

MOD: CM_SGX (48004b00)

  20 => 00000001

MOD: CM_WKUP (48004c00)

  20 => 000002ff  40 => 00000014

MOD: CM_CCR (48004d00)

  00 => 00370007  04 => 00000011  20 => 00000003  30 => 00000001

  40 => 08c80c00  44 => 0481b00c  48 => 00000009  50 => 00000001

  70 => 00000003

MOD: CM_DSS (48004e00)

  20 => 00000003  40 => 00000404

MOD: CM_CAM (48004f00)

  20 => 00000001  40 => 00000004

MOD: CM_PER (48005000)

  20 => 0007ffff

MOD: CM_EMU (48005100)

  40 => 04040a50  48 => 00000002  4c => 00000001

MOD: CM_NEON (48005300)

MOD: CM_USB (48005400)

  20 => 00000003

MOD: PRM_IVA2 (48316000)

  50 => 00000007  e0 => 00ff0f04  f8 => 00000002

MOD: PRM_OCP (48306800)

  04 => 00000010  14 => 00000001  18 => 00000210  1c => 00000201

MOD: PRM_MPU (48306900)

  58 => 0000000c  d4 => 00000012  e0 => 00030104  e4 => 000000c7

MOD: PRM_CORE (48306a00)

  58 => 00000304  a0 => c33ffe18  a4 => c33ffe18  e0 => 000f0314

  e4 => 000000f7  f0 => 00000004  f8 => 00000004

MOD: PRM_SGX (48306b00)

  e0 => 00030104

MOD: PRM_WKUP (48306c00)

  a0 => 0000010b  a4 => 0000010b  b0 => 00010100

MOD: PRM_CCR (48306d00)

  40 => 00000003

MOD: PRM_DSS (48306e00)

  a0 => 00000001  e0 => 00030104

MOD: PRM_CAM (48306f00)

  58 => 00000001  e0 => 00030104

MOD: PRM_PER (48307000)

  58 => 0000000c  a0 => 0003e807  a4 => 0003e807  c8 => 00000007

  e0 => 00030104

MOD: PRM_EMU (48307100)

  58 => 00000004  e4 => 00000103

MOD: PRM_GLBL (48307200)

  20 => 00120012  24 => 00010000  2c => 28201e00  30 => 2b201e00

  34 => 00120000  38 => 00000008  54 => 00001006  58 => 00000001

  60 => 00000004  64 => 00000050  70 => 00000048  90 => 0fff0fff

  94 => 000000ff  98 => 000000ff  9c => 00000002  a0 => 000000ff

  b0 => 00202808  b4 => 0001f401  b8 => 0001f404  bc => 3c00ffff

  c0 => 00000028  c4 => 00000001  d0 => 00202b08  d4 => 0001f401

  d8 => 0001f404  dc => 2c00ffff  e0 => 0000002b  e4 => 00000001

MOD: PRM_NEON (48307300)

  58 => 0000000c  c8 => 00000002  e0 => 00000004  e4 => 00000003

MOD: PRM_USB (48307400)

  58 => 00000008  a0 => 00000001  a4 => 00000001  a8 => 00000001

  e0 => 00030104

[root@arago /]#

Hi Kazunobu,

Thanks for the quick reply!  Before I retry my system, could I ask what silicon revision you used for your test?

I'm using:

OMAP3630/DM3730 ES1.0 (l2cache iva sgx neon isp 192mhz_clk )

thanks,

Jeff

Hi Jeff,

The same info was displayed during the boot on my setup. However I know my silicon is ES1.2. 

OMAP3630/DM3730 ES1.0 (l2cache iva sgx neon isp 192mhz_clk )

Please check your silicon revision by the way described in this wiki.

http://processors.wiki.ti.com/index.php/How_to_Find_the_Silicon_Revision_of_your_OMAP35x_or_AM/DM37x

Here is the register value on my setup. My silicon revision is ES1.2.

OMAP3_EVM # md 0x4830a204 1

4830a204: 2b89102f    /..+

Kazunobu,

Ok, I've also got an ES1.2 as well.

Here's what I'm seeing when I suspend without enabling off mode.  Just prior to suspending, my power consumption is about 500 mW.  When I go to RET, I drop down to about 25 mW.

If I enable off mode, my power consumption drops to about 430 mW and my system won't resume.

One of my co-workers created a patch for the kernel to capture the PM and CM registers after a successful suspend.  Below is the state of those registers after a successful suspend to RET and resume from RET:

Suspend Entry Debug Struct: fe40f0ec
Register Name           Value    Expected
PM_PWSTST_IVA2       00000555
*(int *)0xfa3060e4   00000555
PM_PWSTST_SGX        00000000
*(int *)0xfa306be4   00000000
PM_PWSTST_DSS        00000001
*(int *)0xfa306ee4   00000001
PM_PWSTST_CAM        00000001
*(int *)0xfa306fe4   00000001
PM_PWSTST_PER        00000007
*(int *)0xfa3070e4   00000007
PM_PWSTST_NEON       00000003
*(int *)0xfa3073e4   00000003
PM_PWSTST_USBHOST    00000001
*(int *)0xfa3074e4   00000001
CM_IDLEST_IVA2       00000001
*(int *)0xfa004020   00000001
CM_IDLEST_PLL_IVA2   00000000
*(int *)0xfa004024   00000000
CM_IDLEST1_CORE      ffffffbd
*(int *)0xfa004a20   ffffffbd
CM_IDLEST2_CORE      0000001f
*(int *)0xfa004a24   0000001f
CM_IDLEST3_CORE      0000000d
*(int *)0xfa004a28   0000000d
CM_IDLEST_SGX        00000001
*(int *)0xfa004b20   00000001
CM_IDLEST_CKGEN      00000001
*(int *)0xfa004d20   00000001
CM_IDLEST2_CKGEN     00000000
*(int *)0xfa004d24   00000000
CM_IDLEST_DSS        00000003
*(int *)0xfa004e20   00000003
CM_IDLEST_CAM        00000001
*(int *)0xfa004f20   00000001
CM_IDLEST_PER        00041fff
*(int *)0xfa005020   00041fff
CM_IDLEST_NEON       00000000
*(int *)0xfa005320   00000000
CM_IDLEST_USBHOST    00000003
*(int *)0xfa005420   00000003
PM_WKST1_CORE        00000000
*(int *)0xfa306ab0   00000000
PM_WKST3_CORE        00000000
*(int *)0xfa306ab8   00000000
PM_WKST_WKUP         00010000
*(int *)0xfa306cb0   00010000
PM_WKST_PER          00000000
*(int *)0xfa3070b0   00000000
PM_WKST_USBHOST      00000000
*(int *)0xfa3074b0   00000000
CM_FCLKEN_IVA2       00000000
*(int *)0xfa004000   00000000
CM_FCLKEN1_CORE      00000000
*(int *)0xfa004a00   00000000
CM_FCLKEN3_CORE      00000000
*(int *)0xfa004a08   00000000
CM_FCLKEN_SGX        00000000
*(int *)0xfa004b00   00000000
CM_FCLKEN_DSS        00000000
*(int *)0xfa004e00   00000000
CM_FCLKEN_CAM        00000000
*(int *)0xfa004f00   00000000
CM_FCLKEN_PER        00000000
*(int *)0xfa005000   00000000
CM_FCLKEN_USBHOST    00000000
*(int *)0xfa005400   00000000
CM_ICLKEN1_CORE      00000042
*(int *)0xfa004a10   00000042
CM_AUTOIDLE1_CORE    fffffed9
*(int *)0xfa004a30   fffffed9
CM_ICLKEN3_CORE      00000000
*(int *)0xfa004a18   00000000
CM_AUTOIDLE3_CORE    0000000c
*(int *)0xfa004a38   0000000c
CM_ICLKEN_SGX        00000000
*(int *)0xfa004b10   00000000
CM_ICLKEN_DSS        00000000
*(int *)0xfa004e10   00000000
CM_AUTOIDLE_DSS      00000001
*(int *)0xfa004e30   00000001
CM_ICLKEN_CAM        00000000
*(int *)0xfa004f10   00000000
CM_AUTOIDLE_CAM      00000001
*(int *)0xfa004f30   00000001
CM_ICLKEN_PER        0003e000
*(int *)0xfa005010   0003e000
CM_AUTOIDLE_PER      0003ffff
*(int *)0xfa005030   0003ffff
CM_ICLKEN_USBHOST    00000000
*(int *)0xfa005410   00000000
CM_AUTOIDLE_USBHOST  00000001
*(int *)0xfa005430   00000001
CM_CLKSTCTRL_IVA2    00000003
*(int *)0xfa004048   00000003
*(int *)0xfa004948   00000003
*(int *)0xfa004a48   0000003f
*(int *)0xfa005348   00000003
*(int *)0xfa005448   00000003

Is there anything that you can thing of that could prevent me from entering off if suspending to RET is working?

thanks,

Jeff

Jeff,

The status of those registers looks ok. Is the difference of procedure between suspending to RET or OFF just w/wo enable_off_mode option ?

Yes, the only I do different between the two suspend attempts is to 'echo 1 > enable_off_mode' when I try to suspend to OFF.

Do you have any suggestions on things I could look at?

thanks,

Jeff

1. Can you use a JTAG debugger to step through the code and see where it crashes or gets stucked ?

2. Can you monitor I2C4 communications between the processor and the PMIC on suspend ?

3. Can you check sys_off_mode and sys_clkreq pad configurations ?

Here are my settings for those pads.

[root@arago /]# cat /debug/omap_mux/sys_clkreq

name: sys_clkreq.sys_clkreq (0x48002a06/0x9d6 = 0x0100), b af25, t NA

mode: OMAP_PIN_INPUT | OMAP_MUX_MODE0

signals: sys_clkreq | NA | NA | NA | gpio_1 | NA | NA | safe_mode

[root@arago /]# cat /debug/omap_mux/sys_off_mode

name: sys_off_mode.sys_off_mode (0x48002a18/0x9e8 = 0x0100), b af22, t NA

mode: OMAP_PIN_INPUT | OMAP_MUX_MODE0

signals: sys_off_mode | NA | NA | NA | gpio_9 | NA | NA | safe_mode

Please also check the value of PRM_VOLTCTRL (0x4830 7260). I have 0x2 w/o enable_off_mode and 0x4 w/ enable_off_mode. The VDD1 and VDD2 voltage control on suspend with the OFF mode enabled (w/ enable_off_mode option) is done via I2C4 with 0x4 for PRM_VOLTCTRL. 

Kazunobu,

I'll check out your suggestions and let you know what I find.  It may be a couple of days before I can get back to this.

Thanks,

Jeff