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TDA2SX: Does the configuration of DDR in the MLO file prevent entry to BOOT?

Part Number: TDA2SX
Other Parts Discussed in Thread: TDA2

Hi team,

Here's an issue from the customer may need your help:

Log info of the TDA2S DEMO board: DRAM: 4 GiB. And the self-made reference board is only 2GB.

The customer suspect this will cause the system to enter a dead loop after BOOT is up, and DDR on the DEMO board to EMIF1 also does not work. Is this possible?

Modify the configuration of DDR in the TDA2 MLO file to be configured as one EMIF interface. How to modify the MLO?

Source code: PROCESSOR-SDK-VISION_03.07.01.00 | TI.com

Could you help check this case? Thanks.

Best Regards,

Cherry